247 lines
11 KiB
C
247 lines
11 KiB
C
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/***********************************************************************************************************************
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* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
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*
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* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
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* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
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* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
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* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
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* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
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* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
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* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
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* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
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* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
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* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
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* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
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* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
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* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
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* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Includes <System Includes> , "Project Includes"
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**********************************************************************************************************************/
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#include "r_ioport.h"
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#include "bsp_cfg.h"
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#include "bsp_pin_cfg.h"
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#include "board_sdram.h"
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/* SDRAM size, in bytes */
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#define SDRAM_SIZE (64 * 1024 * 1024)
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/*
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* Set ACTIVE-to-PRECHARGE command (tRAS) timing
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* e.g. tRAS = 42ns -> 6cycles are needed at SDCLK 120MHz
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* tRAS = 37ns -> 5cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRAS (6U)
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/*
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* Set ACTIVE-to-READ or WRITE delay tRCD (tRCD) timing
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* e.g. tRCD = 18ns -> 3cycles are needed at SDCLK 120MHz
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* tRCD = 15ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRCD (3U)
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/*
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* Set PRECHARGE command period (tRP) timing
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* e.g. tRP = 18ns -> 3cycles are needed at SDCLK 120MHz
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* tRP = 15ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRP (3U)
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/*
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* Set WRITE recovery time (tWR) timing
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* e.g. tWR = 1CLK + 6ns -> 2cycles are needed at SDCLK 120MHz
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* tWR = 1CLK + 7ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TWR (2U)
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/*
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* Set CAS (READ) latency (CL) timing
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* e.g. CL = 18ns -> 3cycles are needed at SDCLK 120MHz
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* e.g. CL = 15ns -> 2cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_CL (3U)
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/*
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* Set AUTO REFRESH period (tRFC) timing
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* e.g. tRFC = 60nS -> 8cycles are needed at SDCLK 120MHz
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* tRFC = 66nS -> 8cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_TRFC (8U)
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/*
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* Set Average Refresh period
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* e.g. tREF = 64ms/8192rows -> 7.8125us/each row. 937cycles are needed at SDCLK 120MHz
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*/
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#define BSP_PRV_SDRAM_REF_CMD_INTERVAL (937U)
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/*
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* Set Auto-Refresh issue times in initialization sequence needed for SDRAM device
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* Typical SDR SDRAM device needs twice of Auto-Refresh command issue
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*/
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#define BSP_PRV_SDRAM_SDIR_REF_TIMES (2U)
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/*
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* Set RAW address offset
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* Available settings are
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* 8 : 8-bit
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* 9 : 9-bit
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* 10 : 10-bit
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* 11 : 11-bit
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*/
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#define BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET (9U)
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/*
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* Select endian mode for SDRAM address space
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* 0 : Endian of SDRAM address space is the same as the endian of operating mode
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* 1 : Endian of SDRAM address space is not the endian of operating mode
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*/
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#define BSP_PRV_SDRAM_ENDIAN_MODE (0U)
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/*
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* Select access mode
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* Typically Continuous access should be enabled to get better SDRAM bandwidth
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* 0: Continuous access is disabled
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* 1: Continuous access is enabled
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*/
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#define BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE (1U)
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/*
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* Select bus width
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* 0: 16-bit
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* 1: 32-bit
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* 2: 8-bit
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*/
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#define BSP_PRV_SDRAM_BUS_WIDTH (0U)
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#if ((BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 8U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 9U) \
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&& (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 10U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET > 11U))
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#error "BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET must be either of 8,9,10 or 11"
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#endif
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#if ((BSP_PRV_SDRAM_BUS_WIDTH != 0) && (BSP_PRV_SDRAM_BUS_WIDTH != 1U) && (BSP_PRV_SDRAM_BUS_WIDTH != 2U))
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#error "BSP_PRV_SDRAM_BUS_WIDTH must be either of 0(16-bit) or 1(32-bit) or 2(8-bit)"
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#endif
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#if ((BSP_PRV_SDRAM_ENDIAN_MODE != 0) && (BSP_PRV_SDRAM_ENDIAN_MODE != 1))
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#error \
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"BSP_PRV_SDRAM_ENDIAN_MODE must be either of 0(same endian as operating mode) or 2(another endian against operating mode)"
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#endif
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#if ((BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 0) && (BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 1))
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#error \
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"BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE must be either of 0(continuous access is disabled) or 1(continuous access is enabled)"
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#endif
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#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */
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#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */
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#define BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL (0U) /* MR.M3 Burst Type : Sequential */
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#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global variables (to be accessed by other files)
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Private global variables and functions
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**********************************************************************************************************************/
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void bsp_sdram_init (void)
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{
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/** Setting for SDRAM initialization sequence */
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#if (BSP_PRV_SDRAM_TRP < 3)
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R_BUS->SDRAM.SDIR_b.PRC = 3U;
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#else
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R_BUS->SDRAM.SDIR_b.PRC = BSP_PRV_SDRAM_TRP - 3U;
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#endif
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
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}
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R_BUS->SDRAM.SDIR_b.ARFC = BSP_PRV_SDRAM_SDIR_REF_TIMES;
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
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}
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#if (BSP_PRV_SDRAM_TRFC < 3)
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R_BUS->SDRAM.SDIR_b.ARFI = 0U;
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#else
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R_BUS->SDRAM.SDIR_b.ARFI = BSP_PRV_SDRAM_TRFC - 3U;
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#endif
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */
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}
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/** Start SDRAM initialization sequence.
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* Following operation is automatically done when set SDICR.INIRQ bit.
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* Perform a PRECHARGE ALL command and wait at least tRP time.
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* Issue an AUTO REFRESH command and wait at least tRFC time.
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* Issue an AUTO REFRESH command and wait at least tRFC time.
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*/
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R_BUS->SDRAM.SDICR_b.INIRQ = 1U;
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while (R_BUS->SDRAM.SDSR_b.INIST)
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{
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/* Wait the end of initialization sequence. */
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}
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/** Setting for SDRAM controller */
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R_BUS->SDRAM.SDCCR_b.BSIZE = BSP_PRV_SDRAM_BUS_WIDTH; /* set SDRAM bus width */
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R_BUS->SDRAM.SDAMOD_b.BE = BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE; /* enable continuous access */
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R_BUS->SDRAM.SDCMOD_b.EMODE = BSP_PRV_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */
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}
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/** Using LMR command, program the mode register */
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R_BUS->SDRAM.SDMOD = ((((uint16_t) (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) |
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(uint16_t) (BSP_PRV_SDRAM_MR_OP_MODE << 7)) |
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(uint16_t) (BSP_PRV_SDRAM_CL << 4)) |
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(uint16_t) (BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL << 3)) |
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(uint16_t) (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0);
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/** wait at least tMRD time */
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while (R_BUS->SDRAM.SDSR_b.MRSST)
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{
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/* Wait until Mode Register setting done. */
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}
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/** Set timing parameters for SDRAM */
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R_BUS->SDRAM.SDTR_b.RAS = BSP_PRV_SDRAM_TRAS - 1U; /* set ACTIVE-to-PRECHARGE command cycles*/
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R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */
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R_BUS->SDRAM.SDTR_b.RP = BSP_PRV_SDRAM_TRP - 1U; /* set PRECHARGE command period cycles */
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R_BUS->SDRAM.SDTR_b.WR = BSP_PRV_SDRAM_TWR - 1U; /* set write recovery cycles */
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R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */
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/** Set row address offset for target SDRAM */
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R_BUS->SDRAM.SDADR_b.MXC = BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET - 8U;
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R_BUS->SDRAM.SDRFCR_b.REFW = (uint16_t) (BSP_PRV_SDRAM_TRFC - 1U); /* set Auto-Refresh issuing cycle */
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R_BUS->SDRAM.SDRFCR_b.RFC = BSP_PRV_SDRAM_REF_CMD_INTERVAL - 1U; /* set Auto-Refresh period */
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/** Start Auto-refresh */
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R_BUS->SDRAM.SDRFEN_b.RFEN = 1U;
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/** Enable SDRAM access */
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R_BUS->SDRAM.SDCCR_b.EXENB = 1U;
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}
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