2022-12-07 11:13:25 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-09 shelton first version
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2023-01-30 09:44:30 +08:00
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* 2023-01-31 shelton add support f421/f425
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2023-04-07 14:25:06 +08:00
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* 2023-04-08 shelton add support f423
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2022-12-07 11:13:25 +08:00
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*/
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#ifndef __DRV_DMA_H__
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#define __DRV_DMA_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rtdevice.h>
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#include <rtthread.h>
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#include "drv_common.h"
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#define DMA_GLO_FLAG 0x0001U
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#define DMA_FDT_FLAG 0x0002U
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#define DMA_HDT_FLAG 0x0004U
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#define DMA_DTE_FLAG 0x0008U
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struct dma_config {
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dma_type *dma_x;
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rt_uint8_t channel_index;
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rt_bool_t dma_done;
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dma_channel_type *dma_channel;
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crm_periph_clock_type dma_clock;
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IRQn_Type dma_irqn;
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2023-01-30 09:44:30 +08:00
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#if defined (SOC_SERIES_AT32F425)
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rt_uint8_t flex_channel;
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rt_uint32_t request_id;
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#endif
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2023-04-07 14:25:06 +08:00
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#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
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2023-11-09 16:38:19 +08:00
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defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
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defined (SOC_SERIES_AT32F405)
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2022-12-07 11:13:25 +08:00
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dmamux_channel_type *dmamux_channel;
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rt_uint32_t request_id;
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#endif
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /*__DRV_DMA_H__ */
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/************************** end of file ******************/
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