582 lines
18 KiB
C
582 lines
18 KiB
C
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/*
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* STM32 Eth Driver for RT-Thread
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* Change Logs:
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* Date Author Notes
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* 2009-10-05 Bernard eth interface driver for STM32F107 CL
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*/
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include "lwipopts.h"
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#include "stm32f2x7_eth.h"
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#include "stm32f2x7_eth_conf.h"
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#define STM32_ETH_DEBUG 0
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#define CHECKSUM_BY_HARDWARE
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/* MII and RMII mode selection, for STM322xG-EVAL Board(MB786) RevB ***********/
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//#define MII_MODE
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#define RMII_MODE // In this case the System clock frequency is configured
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// to 100 MHz, for more details refer to system_stm32f2xx.c
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#define DP83848_PHY_ADDRESS 0x01 /* Relative to STM322xG-EVAL Board */
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#define netifGUARD_BLOCK_TIME 250
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/* Ethernet Rx & Tx DMA Descriptors */
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extern ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
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/* Ethernet Receive buffers */
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extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];
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/* Ethernet Transmit buffers */
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extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
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/* Global pointers to track current transmit and receive descriptors */
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extern ETH_DMADESCTypeDef *DMATxDescToSet;
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extern ETH_DMADESCTypeDef *DMARxDescToGet;
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/* Global pointer for last received frame infos */
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extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;
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#define MAX_ADDR_LEN 6
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struct rt_stm32_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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};
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static struct rt_stm32_eth stm32_eth_device;
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static struct rt_semaphore tx_wait;
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static rt_bool_t tx_is_waiting = RT_FALSE;
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static void ETH_MACDMA_Config(void);
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static struct rt_semaphore tx_wait;
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/* interrupt service routine */
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void ETH_IRQHandler(void)
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{
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rt_uint32_t status;
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status = ETH->DMASR;
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/* Frame received */
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if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET)
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{
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rt_err_t result;
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//rt_kprintf("Frame comming\n");
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/* Clear the interrupt flags. */
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/* Clear the Eth DMA Rx IT pending bits */
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ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
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/* a frame has been received */
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result = eth_device_ready(&(stm32_eth_device.parent));
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if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result );
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//RT_ASSERT(result == RT_EOK);
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}
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if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
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{
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ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
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}
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ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
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//
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}
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/* RT-Thread Device Interface */
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/* initialize the interface */
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static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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{
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int i;
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/* MAC address configuration */
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ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
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/* Initialize Tx Descriptors list: Chain Mode */
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ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
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/* Initialize Rx Descriptors list: Chain Mode */
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ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
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/* Enable Ethernet Rx interrrupt */
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{
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for(i=0; i<ETH_RXBUFNB; i++)
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{
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ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
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}
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}
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#ifdef CHECKSUM_BY_HARDWARE
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/* Enable the checksum insertion for the Tx frames */
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{
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for(i=0; i<ETH_TXBUFNB; i++)
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{
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ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
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}
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}
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#endif
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{
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uint16_t tmp, i=10000;
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tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
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ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1, BIST_CONT_MODE );
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ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp | BIST_START );//BIST_START
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while(i--);
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//tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
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if( ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR) & BIST_STATUS == BIST_STATUS )
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{
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rt_kprintf("BIST pass\n");
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}
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else
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{
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uint16_t ctrl;
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ctrl = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1);
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rt_kprintf("BIST faild count =%d\n", BIST_ERROR_COUNT(ctrl) );
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}
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tmp &= ~BIST_START; //Stop BIST
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ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp);
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}
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/* Enable MAC and DMA transmission and reception */
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ETH_Start();
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//rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
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// rt_kprintf("ETH Init\n");
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_close(rt_device_t dev)
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{
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return RT_EOK;
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}
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static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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switch(cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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void show_frame(struct pbuf *q)
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{
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int i = 0;
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int j = 0;
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char *ptr = q->payload;
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for( i = 0; i < q->len; i++ )
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rt_kprintf("0x%02X ", *(ptr++));
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rt_kprintf("\n");
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}
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/* ethernet device interface */
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/* transmit packet. */
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rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
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{
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rt_err_t ret;
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struct pbuf *q;
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uint32_t l = 0;
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u8 *buffer ;
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if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK)
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{
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buffer = (u8 *)(DMATxDescToSet->Buffer1Addr);
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for(q = p; q != NULL; q = q->next)
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{
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//show_frame(q);
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rt_memcpy((u8_t*)&buffer[l], q->payload, q->len);
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l = l + q->len;
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}
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if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR )
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rt_kprintf("Tx Error\n");
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//rt_sem_release(xTxSemaphore);
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rt_sem_release(&tx_wait);
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//rt_kprintf("Tx packet, len = %d\n", l);
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}
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else
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{
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rt_kprintf("Tx Timeout\n");
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return ret;
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}
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/* Return SUCCESS */
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return RT_EOK;
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}
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/* reception packet. */
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struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
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{
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struct pbuf *p, *q;
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u16_t len;
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uint32_t l=0,i =0;
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FrameTypeDef frame;
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static framecnt = 1;
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u8 *buffer;
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__IO ETH_DMADESCTypeDef *DMARxNextDesc;
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p = RT_NULL;
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// rt_kprintf("ETH rx\n");
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/* Get received frame */
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frame = ETH_Get_Received_Frame_interrupt();
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if( frame.length > 0 )
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{
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/* check that frame has no error */
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if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET)
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{
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//rt_kprintf("Get a frame %d buf = 0x%X, len= %d\n", framecnt++, frame.buffer, frame.length);
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/* Obtain the size of the packet and put it into the "len" variable. */
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len = frame.length;
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buffer = (u8 *)frame.buffer;
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/* We allocate a pbuf chain of pbufs from the pool. */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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//p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
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/* Copy received frame from ethernet driver buffer to stack buffer */
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if (p != NULL)
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{
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for (q = p; q != NULL; q = q->next)
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{
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rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len);
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l = l + q->len;
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}
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}
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}
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/* Release descriptors to DMA */
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/* Check if received frame with multiple DMA buffer segments */
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if (DMA_RX_FRAME_infos->Seg_Count > 1)
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{
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DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc;
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}
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else
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{
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DMARxNextDesc = frame.descriptor;
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}
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/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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for (i=0; i<DMA_RX_FRAME_infos->Seg_Count; i++)
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{
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DMARxNextDesc->Status = ETH_DMARxDesc_OWN;
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DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr);
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}
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/* Clear Segment_Count */
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DMA_RX_FRAME_infos->Seg_Count =0;
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/* When Rx Buffer unavailable flag is set: clear it and resume reception */
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if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
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{
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/* Clear RBUS ETHERNET DMA flag */
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ETH->DMASR = ETH_DMASR_RBUS;
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/* Resume DMA reception */
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ETH->DMARPDR = 0;
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}
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}
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return p;
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}
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static void NVIC_Configuration(void)
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{
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NVIC_InitTypeDef NVIC_InitStructure;
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/* 2 bit for pre-emption priority, 2 bits for subpriority */
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NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
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/* Enable the Ethernet global Interrupt */
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NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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}
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/*
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* GPIO Configuration for ETH
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*/
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static void GPIO_Configuration(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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/* Enable GPIOs clocks */
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
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RCC_AHB1Periph_GPIOC
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, ENABLE);
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/* Enable SYSCFG clock */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
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/* Configure MCO (PA8) */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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//GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_MCO );
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#ifdef MII_MODE
|
||
|
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/* Output PLL clock divided by 2 (25MHz) on MCO pin (PA8) to clock the PHY */
|
||
|
|
RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1);
|
||
|
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|
||
|
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SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_MII);
|
||
|
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#elif defined RMII_MODE
|
||
|
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/* Output PLL clock divided by 2 (50MHz) on MCO pin (PA8) to clock the PHY */
|
||
|
|
//RCC_MCO1Config(RCC_MCO1Source_PLLCLK, RCC_MCO1Div_2);
|
||
|
|
|
||
|
|
SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Ethernet pins configuration ************************************************/
|
||
|
|
|
||
|
|
/*
|
||
|
|
ETH_MDIO -------------------------> PA2
|
||
|
|
ETH_MDC --------------------------> PC1
|
||
|
|
ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1
|
||
|
|
ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7
|
||
|
|
ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4
|
||
|
|
ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5
|
||
|
|
ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PB11
|
||
|
|
ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12
|
||
|
|
ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13
|
||
|
|
|
||
|
|
**** Just for MII Mode ****
|
||
|
|
ETH_MII_CRS ----------------------> PA0
|
||
|
|
ETH_MII_COL ----------------------> PA3
|
||
|
|
ETH_MII_TX_CLK -------------------> PC3
|
||
|
|
ETH_MII_RX_ER --------------------> PB10
|
||
|
|
ETH_MII_RXD2 ---------------------> PB0
|
||
|
|
ETH_MII_RXD3 ---------------------> PB1
|
||
|
|
ETH_MII_TXD2 ---------------------> PC2
|
||
|
|
ETH_MII_TXD3 ---------------------> PB8
|
||
|
|
*/
|
||
|
|
/* Configure PC1, PC4 and PC5 */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_4 | GPIO_Pin_5;
|
||
|
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
|
||
|
|
|
||
|
|
/* Configure PB11, PB12 and PB13 */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
|
||
|
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
|
||
|
|
|
||
|
|
/* Configure PA1, PA2 and PA7 */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2 | GPIO_Pin_7;
|
||
|
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
|
||
|
|
|
||
|
|
#ifdef MII_MODE
|
||
|
|
/* Configure PC2, PC3 */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 |GPIO_Pin_3;
|
||
|
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH);
|
||
|
|
|
||
|
|
/* Configure PB0, PB1, PB10 and PB8 */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1, GPIO_Pin_10 | GPIO_Pin_8;
|
||
|
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH);
|
||
|
|
|
||
|
|
/* Configure PA0, PA3 */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_3;
|
||
|
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_ETH);
|
||
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configures the Ethernet Interface
|
||
|
|
* @param None
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void ETH_MACDMA_Config(void)
|
||
|
|
{
|
||
|
|
ETH_InitTypeDef ETH_InitStructure;
|
||
|
|
|
||
|
|
/* Enable ETHERNET clock */
|
||
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
|
||
|
|
RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
|
||
|
|
|
||
|
|
/* Reset ETHERNET on AHB Bus */
|
||
|
|
ETH_DeInit();
|
||
|
|
|
||
|
|
/* Software reset */
|
||
|
|
ETH_SoftwareReset();
|
||
|
|
|
||
|
|
/* Wait for software reset */
|
||
|
|
while (ETH_GetSoftwareResetStatus() == SET);
|
||
|
|
|
||
|
|
/* ETHERNET Configuration --------------------------------------------------*/
|
||
|
|
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
|
||
|
|
ETH_StructInit(Ð_InitStructure);
|
||
|
|
|
||
|
|
/* Fill ETH_InitStructure parametrs */
|
||
|
|
/*------------------------ MAC -----------------------------------*/
|
||
|
|
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
||
|
|
//ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
|
||
|
|
// ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
|
||
|
|
// ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
|
||
|
|
|
||
|
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
||
|
|
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
|
||
|
|
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
||
|
|
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
||
|
|
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
|
||
|
|
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
|
||
|
|
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
||
|
|
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
||
|
|
#ifdef CHECKSUM_BY_HARDWARE
|
||
|
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*------------------------ DMA -----------------------------------*/
|
||
|
|
|
||
|
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
||
|
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
||
|
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
||
|
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
||
|
|
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
||
|
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
||
|
|
|
||
|
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
|
||
|
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
|
||
|
|
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
|
||
|
|
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
||
|
|
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
|
||
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
||
|
|
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
||
|
|
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
|
||
|
|
|
||
|
|
/* Configure Ethernet */
|
||
|
|
if( ETH_Init(Ð_InitStructure, DP83848_PHY_ADDRESS) == ETH_ERROR )
|
||
|
|
rt_kprintf("ETH init error, may be no link\n");
|
||
|
|
|
||
|
|
/* Enable the Ethernet Rx Interrupt */
|
||
|
|
ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R , ENABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define DevID_SNo0 (*((rt_uint32_t *)0x1FFF7A10));
|
||
|
|
#define DevID_SNo1 (*((rt_uint32_t *)0x1FFF7A10+32));
|
||
|
|
#define DevID_SNo2 (*((rt_uint32_t *)0x1FFF7A10+64));
|
||
|
|
void rt_hw_stm32_eth_init(void)
|
||
|
|
{
|
||
|
|
GPIO_Configuration();
|
||
|
|
NVIC_Configuration();
|
||
|
|
ETH_MACDMA_Config();
|
||
|
|
|
||
|
|
stm32_eth_device.dev_addr[0] = 0x00;
|
||
|
|
stm32_eth_device.dev_addr[1] = 0x60;
|
||
|
|
stm32_eth_device.dev_addr[2] = 0x6e;
|
||
|
|
{
|
||
|
|
uint32_t cpu_id[3] = {0};
|
||
|
|
cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0;
|
||
|
|
|
||
|
|
// generate MAC addr from 96bit unique ID (only for test)
|
||
|
|
stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF);
|
||
|
|
stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF);
|
||
|
|
stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF);
|
||
|
|
|
||
|
|
// stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7);
|
||
|
|
// stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8);
|
||
|
|
// stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9);
|
||
|
|
}
|
||
|
|
|
||
|
|
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
||
|
|
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
|
||
|
|
stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
|
||
|
|
stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
|
||
|
|
stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
|
||
|
|
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
|
||
|
|
stm32_eth_device.parent.parent.user_data = RT_NULL;
|
||
|
|
|
||
|
|
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
|
||
|
|
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
|
||
|
|
|
||
|
|
/* init tx semaphore */
|
||
|
|
rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO);
|
||
|
|
|
||
|
|
/* register eth device */
|
||
|
|
eth_device_init(&(stm32_eth_device.parent), "e0");
|
||
|
|
}
|
||
|
|
static char led = 0;
|
||
|
|
|
||
|
|
void dp83483()
|
||
|
|
{
|
||
|
|
uint16_t bsr,sts, bcr, phycr;
|
||
|
|
|
||
|
|
bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR);
|
||
|
|
sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR);
|
||
|
|
bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR);
|
||
|
|
phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
|
||
|
|
|
||
|
|
rt_kprintf("BCR = 0x%X\tBSR = 0x%X\tPHY_STS = 0x%X\tPHY_CR = 0x%X\n", bcr,bsr,sts, phycr);
|
||
|
|
|
||
|
|
rt_kprintf("PHY_FCSCR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR ) );
|
||
|
|
rt_kprintf("PHY_MISR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) );
|
||
|
|
|
||
|
|
rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
|
||
|
|
|
||
|
|
//ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led));
|
||
|
|
led = (led==7)?0:7;
|
||
|
|
|
||
|
|
}
|
||
|
|
#ifdef RT_USING_FINSH
|
||
|
|
#include <finsh.h>
|
||
|
|
FINSH_FUNCTION_EXPORT(dp83483, Show PHY register.);
|
||
|
|
#endif
|