685 lines
17 KiB
C
685 lines
17 KiB
C
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/**************************************************************************//**
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* @file core_cmInstr.h
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* @brief CMSIS Cortex-M Core Instruction Access Header File
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* @version V1.40
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* @date 16. February 2010
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*
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* @note
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* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __CORE_CMINSTR_H__
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#define __CORE_CMINSTR_H__
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/* ########################## Core Instruction Access ######################### */
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#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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/* ARM armcc specific functions */
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/**
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* @brief No Operation
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*
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* No Operation does nothing. This instruction can be used for code alignment
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* purposes.
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*/
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#define __NOP __nop
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/**
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* @brief Wait For Interrupt
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*
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* Wait For Interrupt is a hint instruction that suspends execution until
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* one of a number of events occurs.
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*/
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#define __WFI __wfi
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/**
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* @brief Wait For Event
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*
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* Wait For Event is a hint instruction that permits the processor to enter
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* a low-power state until one of a number of events occurs.
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*/
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#define __WFE __wfe
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/**
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* @brief Send Event
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*
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* Send Event is a hint instruction. It causes an event to be signaled
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* to the CPU.
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*/
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#define __SEV __sev
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/**
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* @brief Instruction Synchronization Barrier
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*
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* Instruction Synchronization Barrier flushes the pipeline in the processor,
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* so that all instructions following the ISB are fetched from cache or
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* memory, after the instruction has been completed
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*/
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#define __ISB() __isb(0xF)
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/**
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* @brief Data Synchronization Barrier
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*
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* The DSB instruction operation acts as a special kind of Data Memory Barrier.
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* The DSB operation completes when all explicit memory accesses before this
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* instruction complete.
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*/
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#define __DSB() __dsb(0xF)
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/**
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* @brief Data Memory Barrier
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*
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* DMB ensures the apparent order of the explicit memory operations before
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* and after the instruction, without ensuring their completion.
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*/
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#define __DMB() __dmb(0xF)
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/**
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* @brief Reverse byte order (32 bit)
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in integer value
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*/
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#define __REV __rev
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/**
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* @brief Reverse byte order (16 bit)
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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#if (__ARMCC_VERSION < 400677)
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extern uint32_t __REV16(uint16_t value);
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#else /* (__ARMCC_VERSION >= 400677) */
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static __INLINE __ASM uint32_t __REV16(uint16_t value)
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{
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rev16 r0, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Reverse byte order in signed short value with sign extension to integer
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in signed short value with sign extension to integer
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*/
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#if (__ARMCC_VERSION < 400677)
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extern int32_t __REVSH(int16_t value);
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#else /* (__ARMCC_VERSION >= 400677) */
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static __INLINE __ASM int32_t __REVSH(int16_t value)
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{
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revsh r0, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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#if (__CORTEX_M >= 0x03)
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/**
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* @brief Reverse bit order of value
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse bit order of value
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*/
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#define __RBIT __rbit
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/**
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* @brief LDR Exclusive (8 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 8 bit value
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*/
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#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
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/**
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* @brief LDR Exclusive (16 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 16 bit values
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*/
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#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
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/**
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* @brief LDR Exclusive (32 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 32 bit values
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*/
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#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
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/**
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* @brief STR Exclusive (8 bit)
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*
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* @param value value to store
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* @param *addr address pointer
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* @return successful / failed
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*
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* Exclusive STR command for 8 bit values
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*/
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#define __STREXB(value, ptr) __strex(value, ptr)
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/**
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* @brief STR Exclusive (16 bit)
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*
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* @param value value to store
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* @param *addr address pointer
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* @return successful / failed
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*
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* Exclusive STR command for 16 bit values
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*/
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#define __STREXH(value, ptr) __strex(value, ptr)
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/**
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* @brief STR Exclusive (32 bit)
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*
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* @param value value to store
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* @param *addr address pointer
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* @return successful / failed
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*
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* Exclusive STR command for 32 bit values
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*/
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#define __STREXW(value, ptr) __strex(value, ptr)
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/**
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* @brief Remove the exclusive lock created by ldrex
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*
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* Removes the exclusive lock which is created by ldrex.
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __CLREX(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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#define __CLREX __clrex
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#endif /* __ARMCC_VERSION */
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#endif /* (__CORTEX_M >= 0x03) */
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#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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/* IAR iccarm specific functions */
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#if defined (__ICCARM__)
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#include <intrinsics.h> /* IAR Intrinsics */
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#endif
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#pragma diag_suppress=Pe940
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/**
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* @brief No Operation
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*
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* No Operation does nothing. This instruction can be used for code alignment
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* purposes.
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*/
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#define __NOP __no_operation
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/**
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* @brief Wait For Interrupt
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*
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* Wait For Interrupt is a hint instruction that suspends execution until
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* one of a number of events occurs.
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*/
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static __INLINE void __WFI() { __ASM ("wfi"); }
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/**
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* @brief Wait For Event
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*
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* Wait For Event is a hint instruction that permits the processor to enter
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* a low-power state until one of a number of events occurs.
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*/
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static __INLINE void __WFE() { __ASM ("wfe"); }
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/**
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* @brief Send Event
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*
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* Send Event is a hint instruction. It causes an event to be signaled
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* to the CPU.
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*/
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static __INLINE void __SEV() { __ASM ("sev"); }
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/**
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* @brief Instruction Synchronization Barrier
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*
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* Instruction Synchronization Barrier flushes the pipeline in the processor,
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* so that all instructions following the ISB are fetched from cache or
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* memory, after the instruction has been completed
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*/
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/* intrinsic void __ISB(void) (see intrinsics.h */
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/**
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* @brief Data Synchronization Barrier
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*
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* The DSB instruction operation acts as a special kind of Data Memory Barrier.
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* The DSB operation completes when all explicit memory accesses before this
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* instruction complete.
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*/
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/* intrinsic void __DSB(void) (see intrinsics.h */
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/**
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* @brief Data Memory Barrier
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*
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* DMB ensures the apparent order of the explicit memory operations before
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* and after the instruction, without ensuring their completion.
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*/
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/* intrinsic void __DMB(void) (see intrinsics.h */
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/**
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* @brief Reverse byte order (32 bit)
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in integer value
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*/
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/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */
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/**
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* @brief Reverse byte order (16 bit)
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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static uint32_t __REV16(uint16_t value)
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{
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__ASM("rev16 r0, r0");
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}
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/**
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* @brief Reverse byte order in signed short value with sign extension to integer
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in signed short value with sign extension to integer
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*/
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/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
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#if (__CORTEX_M >= 0x03)
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/**
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* @brief Reverse bit order of value
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse bit order of value
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*/
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static uint32_t __RBIT(uint32_t value)
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{
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__ASM("rbit r0, r0");
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}
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/**
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* @brief LDR Exclusive (8 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 8 bit value
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*/
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static uint8_t __LDREXB(uint8_t *addr)
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{
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__ASM("ldrexb r0, [r0]");
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}
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/**
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* @brief LDR Exclusive (16 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 16 bit values
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*/
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static uint16_t __LDREXH(uint16_t *addr)
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{
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__ASM("ldrexh r0, [r0]");
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}
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/**
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* @brief LDR Exclusive (32 bit)
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*
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* @param *addr address pointer
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* @return value of (*address)
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*
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* Exclusive LDR command for 32 bit values
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*/
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/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */
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static uint32_t __LDREXW(uint32_t *addr)
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{
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__ASM("ldrex r0, [r0]");
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}
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/**
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* @brief STR Exclusive (8 bit)
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*
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* @param value value to store
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* @param *addr address pointer
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* @return successful / failed
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*
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* Exclusive STR command for 8 bit values
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*/
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static uint32_t __STREXB(uint8_t value, uint8_t *addr)
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{
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__ASM("strexb r0, r0, [r1]");
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}
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/**
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* @brief STR Exclusive (16 bit)
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*
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* @param value value to store
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* @param *addr address pointer
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* @return successful / failed
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*
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* Exclusive STR command for 16 bit values
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*/
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static uint32_t __STREXH(uint16_t value, uint16_t *addr)
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{
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__ASM("strexh r0, r0, [r1]");
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}
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/**
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* @brief STR Exclusive (32 bit)
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*
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* @param value value to store
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|
* @param *addr address pointer
|
||
|
|
* @return successful / failed
|
||
|
|
*
|
||
|
|
* Exclusive STR command for 32 bit values
|
||
|
|
*/
|
||
|
|
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */
|
||
|
|
static uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||
|
|
{
|
||
|
|
__ASM("strex r0, r0, [r1]");
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Remove the exclusive lock created by ldrex
|
||
|
|
*
|
||
|
|
* Removes the exclusive lock which is created by ldrex.
|
||
|
|
*/
|
||
|
|
static __INLINE void __CLREX() { __ASM ("clrex"); }
|
||
|
|
|
||
|
|
#endif /* (__CORTEX_M >= 0x03) */
|
||
|
|
|
||
|
|
#pragma diag_default=Pe940
|
||
|
|
|
||
|
|
|
||
|
|
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||
|
|
/* GNU gcc specific functions */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief No Operation
|
||
|
|
*
|
||
|
|
* No Operation does nothing. This instruction can be used for code alignment
|
||
|
|
* purposes.
|
||
|
|
*/
|
||
|
|
static __INLINE void __NOP() { __ASM volatile ("nop"); }
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Wait For Interrupt
|
||
|
|
*
|
||
|
|
* Wait For Interrupt is a hint instruction that suspends execution until
|
||
|
|
* one of a number of events occurs.
|
||
|
|
*/
|
||
|
|
static __INLINE void __WFI() { __ASM volatile ("wfi"); }
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Wait For Event
|
||
|
|
*
|
||
|
|
* Wait For Event is a hint instruction that permits the processor to enter
|
||
|
|
* a low-power state until one of a number of events occurs.
|
||
|
|
*/
|
||
|
|
static __INLINE void __WFE() { __ASM volatile ("wfe"); }
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Send Event
|
||
|
|
*
|
||
|
|
* Send Event is a hint instruction. It causes an event to be signaled
|
||
|
|
* to the CPU.
|
||
|
|
*/
|
||
|
|
static __INLINE void __SEV() { __ASM volatile ("sev"); }
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Instruction Synchronization Barrier
|
||
|
|
*
|
||
|
|
* Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||
|
|
* so that all instructions following the ISB are fetched from cache or
|
||
|
|
* memory, after the instruction has been completed
|
||
|
|
*/
|
||
|
|
static __INLINE void __ISB() { __ASM volatile ("isb"); }
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Data Synchronization Barrier
|
||
|
|
*
|
||
|
|
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
|
||
|
|
* The DSB operation completes when all explicit memory accesses before this
|
||
|
|
* instruction complete.
|
||
|
|
*/
|
||
|
|
static __INLINE void __DSB() { __ASM volatile ("dsb"); }
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Data Memory Barrier
|
||
|
|
*
|
||
|
|
* DMB ensures the apparent order of the explicit memory operations before
|
||
|
|
* and after the instruction, without ensuring their completion.
|
||
|
|
*/
|
||
|
|
static __INLINE void __DMB() { __ASM volatile ("dmb"); }
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Reverse byte order (32 bit)
|
||
|
|
*
|
||
|
|
* @param value value to reverse
|
||
|
|
* @return reversed value
|
||
|
|
*
|
||
|
|
* Reverse byte order in integer value
|
||
|
|
*/
|
||
|
|
static __INLINE uint32_t __REV(uint32_t value)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Reverse byte order (16 bit)
|
||
|
|
*
|
||
|
|
* @param value value to reverse
|
||
|
|
* @return reversed value
|
||
|
|
*
|
||
|
|
* Reverse byte order in unsigned short value
|
||
|
|
*/
|
||
|
|
static __INLINE uint32_t __REV16(uint16_t value)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Reverse byte order in signed short value with sign extension to integer
|
||
|
|
*
|
||
|
|
* @param value value to reverse
|
||
|
|
* @return reversed value
|
||
|
|
*
|
||
|
|
* Reverse byte order in signed short value with sign extension to integer
|
||
|
|
*/
|
||
|
|
static __INLINE int32_t __REVSH(int16_t value)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#if (__CORTEX_M >= 0x03)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Reverse bit order of value
|
||
|
|
*
|
||
|
|
* @param value value to reverse
|
||
|
|
* @return reversed value
|
||
|
|
*
|
||
|
|
* Reverse bit order of value
|
||
|
|
*/
|
||
|
|
static __INLINE uint32_t __RBIT(uint32_t value)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief LDR Exclusive (8 bit)
|
||
|
|
*
|
||
|
|
* @param *addr address pointer
|
||
|
|
* @return value of (*address)
|
||
|
|
*
|
||
|
|
* Exclusive LDR command for 8 bit value
|
||
|
|
*/
|
||
|
|
static __INLINE uint8_t __LDREXB(uint8_t *addr)
|
||
|
|
{
|
||
|
|
uint8_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief LDR Exclusive (16 bit)
|
||
|
|
*
|
||
|
|
* @param *addr address pointer
|
||
|
|
* @return value of (*address)
|
||
|
|
*
|
||
|
|
* Exclusive LDR command for 16 bit values
|
||
|
|
*/
|
||
|
|
static __INLINE uint16_t __LDREXH(uint16_t *addr)
|
||
|
|
{
|
||
|
|
uint16_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief LDR Exclusive (32 bit)
|
||
|
|
*
|
||
|
|
* @param *addr address pointer
|
||
|
|
* @return value of (*address)
|
||
|
|
*
|
||
|
|
* Exclusive LDR command for 32 bit values
|
||
|
|
*/
|
||
|
|
static __INLINE uint32_t __LDREXW(uint32_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief STR Exclusive (8 bit)
|
||
|
|
*
|
||
|
|
* @param value value to store
|
||
|
|
* @param *addr address pointer
|
||
|
|
* @return successful / failed
|
||
|
|
*
|
||
|
|
* Exclusive STR command for 8 bit values
|
||
|
|
*/
|
||
|
|
static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief STR Exclusive (16 bit)
|
||
|
|
*
|
||
|
|
* @param value value to store
|
||
|
|
* @param *addr address pointer
|
||
|
|
* @return successful / failed
|
||
|
|
*
|
||
|
|
* Exclusive STR command for 16 bit values
|
||
|
|
*/
|
||
|
|
static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief STR Exclusive (32 bit)
|
||
|
|
*
|
||
|
|
* @param value value to store
|
||
|
|
* @param *addr address pointer
|
||
|
|
* @return successful / failed
|
||
|
|
*
|
||
|
|
* Exclusive STR command for 32 bit values
|
||
|
|
*/
|
||
|
|
static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result=0;
|
||
|
|
|
||
|
|
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Remove the exclusive lock created by ldrex
|
||
|
|
*
|
||
|
|
* Removes the exclusive lock which is created by ldrex.
|
||
|
|
*/
|
||
|
|
static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
|
||
|
|
|
||
|
|
#endif /* (__CORTEX_M >= 0x03) */
|
||
|
|
|
||
|
|
|
||
|
|
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||
|
|
/* TASKING carm specific functions */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||
|
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||
|
|
* Including the CMSIS ones.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif // __CORE_CMINSTR_H__
|