373 lines
11 KiB
C
373 lines
11 KiB
C
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#include "rt_stm32f10x_spi.h"
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
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static struct rt_spi_ops stm32_spi_ops =
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{
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configure,
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xfer
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};
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#ifdef USING_SPI1
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static struct stm32_spi_bus stm32_spi_bus_1;
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#endif /* #ifdef USING_SPI1 */
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#ifdef USING_SPI2
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static struct stm32_spi_bus stm32_spi_bus_2;
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#endif /* #ifdef USING_SPI2 */
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#ifdef USING_SPI3
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static struct stm32_spi_bus stm32_spi_bus_3;
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#endif /* #ifdef USING_SPI3 */
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//------------------ DMA ------------------
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#ifdef SPI_USE_DMA
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static uint8_t dummy = 0xFF;
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#endif
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#ifdef SPI_USE_DMA
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static void DMA_Configuration(struct stm32_spi_bus * stm32_spi_bus, const void * send_addr, void * recv_addr, rt_size_t size)
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_ClearFlag(stm32_spi_bus->DMA_Channel_RX_FLAG_TC
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| stm32_spi_bus->DMA_Channel_RX_FLAG_TE
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| stm32_spi_bus->DMA_Channel_TX_FLAG_TC
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| stm32_spi_bus->DMA_Channel_TX_FLAG_TE);
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/* RX channel configuration */
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DMA_Cmd(stm32_spi_bus->DMA_Channel_RX, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(stm32_spi_bus->SPI->DR));
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_InitStructure.DMA_BufferSize = size;
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if(recv_addr != RT_NULL)
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{
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) recv_addr;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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}
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else
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{
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) (&dummy);
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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DMA_Init(stm32_spi_bus->DMA_Channel_RX, &DMA_InitStructure);
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DMA_Cmd(stm32_spi_bus->DMA_Channel_RX, ENABLE);
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/* TX channel configuration */
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DMA_Cmd(stm32_spi_bus->DMA_Channel_TX, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(stm32_spi_bus->SPI->DR));
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_InitStructure.DMA_BufferSize = size;
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if(send_addr != RT_NULL)
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{
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32)send_addr;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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}
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else
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{
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32)(&dummy);;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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DMA_Init(stm32_spi_bus->DMA_Channel_TX, &DMA_InitStructure);
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DMA_Cmd(stm32_spi_bus->DMA_Channel_TX, ENABLE);
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}
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#endif
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rt_inline uint16_t get_spi_BaudRatePrescaler(rt_uint32_t max_hz)
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{
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uint16_t SPI_BaudRatePrescaler;
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/* STM32F10x SPI MAX 18Mhz */
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if(max_hz >= SystemCoreClock/2 && SystemCoreClock/2 <= 18000000)
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{
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
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}
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else if(max_hz >= SystemCoreClock/4)
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{
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
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}
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else if(max_hz >= SystemCoreClock/8)
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{
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
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}
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else if(max_hz >= SystemCoreClock/16)
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{
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
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}
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else if(max_hz >= SystemCoreClock/32)
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{
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;
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}
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else if(max_hz >= SystemCoreClock/64)
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{
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
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}
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else if(max_hz >= SystemCoreClock/128)
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{
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_128;
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}
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else
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{
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/* min prescaler 256 */
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SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
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}
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return SPI_BaudRatePrescaler;
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}
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
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{
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struct stm32_spi_bus * stm32_spi_bus = (struct stm32_spi_bus *)device->bus;
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SPI_InitTypeDef SPI_InitStructure;
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SPI_StructInit(&SPI_InitStructure);
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/* data_width */
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if(configuration->data_width <= 8)
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{
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SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
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}
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else if(configuration->data_width <= 16)
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{
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SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
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}
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else
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{
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return RT_EIO;
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}
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/* baudrate */
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SPI_InitStructure.SPI_BaudRatePrescaler = get_spi_BaudRatePrescaler(configuration->max_hz);
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/* CPOL */
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if(configuration->mode & RT_SPI_CPOL)
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{
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SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
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}
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else
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{
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SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
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}
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/* CPHA */
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if(configuration->mode & RT_SPI_CPHA)
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{
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SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
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}
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else
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{
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SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
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}
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/* MSB or LSB */
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if(configuration->mode & RT_SPI_MSB)
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{
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SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
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}
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else
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{
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SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;
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}
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SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
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SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
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SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
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/* init SPI */
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SPI_I2S_DeInit(stm32_spi_bus->SPI);
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SPI_Init(stm32_spi_bus->SPI, &SPI_InitStructure);
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/* Enable SPI_MASTER */
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SPI_Cmd(stm32_spi_bus->SPI, ENABLE);
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SPI_CalculateCRC(stm32_spi_bus->SPI, DISABLE);
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return RT_EOK;
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};
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
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{
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struct stm32_spi_bus * stm32_spi_bus = (struct stm32_spi_bus *)device->bus;
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struct rt_spi_configuration * config = &device->config;
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SPI_TypeDef * SPI = stm32_spi_bus->SPI;
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struct stm32_spi_cs * stm32_spi_cs = device->parent.user_data;
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rt_uint32_t size = message->length;
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/* take CS */
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if(message->cs_take)
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{
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GPIO_ResetBits(stm32_spi_cs->GPIOx, stm32_spi_cs->GPIO_Pin);
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}
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#ifdef SPI_USE_DMA
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if(message->length > 32)
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{
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if(config->data_width <= 8)
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{
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DMA_Configuration(stm32_spi_bus, message->send_buf, message->recv_buf, message->length);
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SPI_I2S_DMACmd(SPI, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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while (DMA_GetFlagStatus(stm32_spi_bus->DMA_Channel_RX_FLAG_TC) == RESET
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|| DMA_GetFlagStatus(stm32_spi_bus->DMA_Channel_TX_FLAG_TC) == RESET);
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SPI_I2S_DMACmd(SPI, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, DISABLE);
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}
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// rt_memcpy(buffer,_spi_flash_buffer,DMA_BUFFER_SIZE);
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// buffer += DMA_BUFFER_SIZE;
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}
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else
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#endif
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{
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if(config->data_width <= 8)
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{
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const rt_uint8_t * send_ptr = message->send_buf;
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rt_uint8_t * recv_ptr = message->recv_buf;
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while(size--)
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{
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rt_uint8_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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//Wait until the transmit buffer is empty
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while (SPI_I2S_GetFlagStatus(SPI, SPI_I2S_FLAG_TXE) == RESET);
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// Send the byte
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SPI_I2S_SendData(SPI, data);
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//Wait until a data is received
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while (SPI_I2S_GetFlagStatus(SPI, SPI_I2S_FLAG_RXNE) == RESET);
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// Get the received data
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data = SPI_I2S_ReceiveData(SPI);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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}
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else if(config->data_width <= 16)
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{
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const rt_uint16_t * send_ptr = message->send_buf;
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rt_uint16_t * recv_ptr = message->recv_buf;
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while(size--)
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{
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rt_uint16_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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//Wait until the transmit buffer is empty
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while (SPI_I2S_GetFlagStatus(SPI, SPI_I2S_FLAG_TXE) == RESET);
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// Send the byte
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SPI_I2S_SendData(SPI, data);
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//Wait until a data is received
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while (SPI_I2S_GetFlagStatus(SPI, SPI_I2S_FLAG_RXNE) == RESET);
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// Get the received data
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data = SPI_I2S_ReceiveData(SPI);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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}
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}
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/* release CS */
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if(message->cs_release)
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{
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GPIO_SetBits(stm32_spi_cs->GPIOx, stm32_spi_cs->GPIO_Pin);
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}
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return message->length;
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};
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/** \brief init and register stm32 spi bus.
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*
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* \param SPI: STM32 SPI, e.g: SPI1,SPI2,SPI3.
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* \param stm32_spi: stm32 spi bus struct.
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* \param spi_bus_name: spi bus name, e.g: "spi1"
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* \return
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*
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*/
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rt_err_t stm32_spi_register(SPI_TypeDef * SPI,
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struct stm32_spi_bus * stm32_spi,
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const char * spi_bus_name)
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{
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
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if(SPI == SPI1)
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{
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stm32_spi->SPI = SPI1;
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#ifdef SPI_USE_DMA
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/* Enable the DMA1 Clock */
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
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stm32_spi->DMA_Channel_RX = DMA1_Channel2;
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stm32_spi->DMA_Channel_TX = DMA1_Channel3;
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stm32_spi->DMA_Channel_RX_FLAG_TC = DMA1_FLAG_TC2;
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stm32_spi->DMA_Channel_RX_FLAG_TE = DMA1_FLAG_TE2;
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stm32_spi->DMA_Channel_TX_FLAG_TC = DMA1_FLAG_TC3;
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stm32_spi->DMA_Channel_TX_FLAG_TE = DMA1_FLAG_TE3;
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#endif
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
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}
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else if(SPI == SPI2)
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{
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stm32_spi->SPI = SPI2;
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#ifdef SPI_USE_DMA
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/* Enable the DMA1 Clock */
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
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stm32_spi->DMA_Channel_RX = DMA1_Channel4;
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stm32_spi->DMA_Channel_TX = DMA1_Channel5;
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stm32_spi->DMA_Channel_RX_FLAG_TC = DMA1_FLAG_TC4;
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stm32_spi->DMA_Channel_RX_FLAG_TE = DMA1_FLAG_TE4;
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stm32_spi->DMA_Channel_TX_FLAG_TC = DMA1_FLAG_TC5;
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stm32_spi->DMA_Channel_TX_FLAG_TE = DMA1_FLAG_TE5;
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#endif
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
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}
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else if(SPI == SPI3)
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{
|
||
|
|
stm32_spi->SPI = SPI3;
|
||
|
|
#ifdef SPI_USE_DMA
|
||
|
|
/* Enable the DMA2 Clock */
|
||
|
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
|
||
|
|
|
||
|
|
stm32_spi->DMA_Channel_RX = DMA2_Channel1;
|
||
|
|
stm32_spi->DMA_Channel_TX = DMA2_Channel2;
|
||
|
|
stm32_spi->DMA_Channel_RX_FLAG_TC = DMA2_FLAG_TC1;
|
||
|
|
stm32_spi->DMA_Channel_RX_FLAG_TE = DMA2_FLAG_TE1;
|
||
|
|
stm32_spi->DMA_Channel_TX_FLAG_TC = DMA2_FLAG_TC2;
|
||
|
|
stm32_spi->DMA_Channel_TX_FLAG_TE = DMA2_FLAG_TE2;
|
||
|
|
#endif
|
||
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
return rt_spi_bus_register(&stm32_spi->parent, spi_bus_name, &stm32_spi_ops);
|
||
|
|
}
|