68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
|
/*
|
||
|
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||
|
|
*
|
||
|
|
* SPDX-License-Identifier: Apache-2.0
|
||
|
|
*
|
||
|
|
* Change Logs:
|
||
|
|
* Date Author Notes
|
||
|
|
* 2023-5-22 Rain Park first version
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include "board.h"
|
||
|
|
|
||
|
|
void SystemClock_Config(void)
|
||
|
|
{
|
||
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||
|
|
|
||
|
|
/** Configure the main internal regulator output voltage
|
||
|
|
*/
|
||
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Configure LSE Drive Capability
|
||
|
|
*/
|
||
|
|
HAL_PWR_EnableBkUpAccess();
|
||
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
|
||
|
|
|
||
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
||
|
|
* in the RCC_OscInitTypeDef structure.
|
||
|
|
*/
|
||
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
|
||
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||
|
|
RCC_OscInitStruct.MSICalibrationValue = 0;
|
||
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_9;
|
||
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||
|
|
RCC_OscInitStruct.PLL.PLLM = 5;
|
||
|
|
RCC_OscInitStruct.PLL.PLLN = 71;
|
||
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
||
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV6;
|
||
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
||
|
|
*/
|
||
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV4;
|
||
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
|
||
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Enable MSI Auto calibration
|
||
|
|
*/
|
||
|
|
HAL_RCCEx_EnableMSIPLLMode();
|
||
|
|
}
|