125 lines
3.4 KiB
C
125 lines
3.4 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fnand_timing.h
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* Date: 2022-04-28 18:53:58
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* LastEditTime: 2022-04-28 18:53:58
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* Description: This file is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#ifndef DRIVERS_NAND_FNAND
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#define DRIVERS_NAND_FNAND
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#include "ftypes.h"
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/**
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* struct FNandSdrTimings - SDR NAND chip timings
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*
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* This struct defines the timing requirements of a SDR NAND chip.
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* These information can be found in every NAND datasheets and the timings
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* meaning are described in the ONFI specifications:
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* www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
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* Parameters)
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*
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* All these timings are expressed in picoseconds.
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*
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* @tBERS_max: Block erase time
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* @tCCS_min: Change column setup time
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* @tPROG_max: Page program time
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* @tR_max: Page read time
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* @tALH_min: ALE hold time
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* @tADL_min: ALE to data loading time
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* @tALS_min: ALE setup time
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* @tAR_min: ALE to RE# delay
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* @tCEA_max: CE# access time
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* @tCEH_min: CE# high hold time
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* @tCH_min: CE# hold time
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* @tCHZ_max: CE# high to output hi-Z
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* @tCLH_min: CLE hold time
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* @tCLR_min: CLE to RE# delay
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* @tCLS_min: CLE setup time
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* @tCOH_min: CE# high to output hold
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* @tCS_min: CE# setup time
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* @tDH_min: Data hold time
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* @tDS_min: Data setup time
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* @tFEAT_max: Busy time for Set Features and Get Features
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* @tIR_min: Output hi-Z to RE# low
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* @tITC_max: Interface and Timing Mode Change time
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* @tRC_min: RE# cycle time
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* @tREA_max: RE# access time
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* @tREH_min: RE# high hold time
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* @tRHOH_min: RE# high to output hold
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* @tRHW_min: RE# high to WE# low
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* @tRHZ_max: RE# high to output hi-Z
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* @tRLOH_min: RE# low to output hold
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* @tRP_min: RE# pulse width
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* @tRR_min: Ready to RE# low (data only)
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* @tRST_max: Device reset time, measured from the falling edge of R/B# to the
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* rising edge of R/B#.
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* @tWB_max: WE# high to SR[6] low
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* @tWC_min: WE# cycle time
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* @tWH_min: WE# high hold time
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* @tWHR_min: WE# high to RE# low
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* @tWP_min: WE# pulse width
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* @tWW_min: WP# transition to WE# low
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*/
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struct FNandSdrTimings
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{
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u64 tBERS_max;
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u32 tCCS_min;
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u64 tPROG_max;
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u64 tR_max;
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u32 tALH_min;
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u32 tADL_min;
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u32 tALS_min;
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u32 tAR_min;
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u32 tCEA_max;
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u32 tCEH_min;
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u32 tCH_min;
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u32 tCHZ_max;
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u32 tCLH_min;
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u32 tCLR_min;
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u32 tCLS_min;
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u32 tCOH_min;
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u32 tCS_min;
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u32 tDH_min;
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u32 tDS_min;
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u32 tFEAT_max;
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u32 tIR_min;
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u32 tITC_max;
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u32 tRC_min;
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u32 tREA_max;
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u32 tREH_min;
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u32 tRHOH_min;
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u32 tRHW_min;
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u32 tRHZ_max;
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u32 tRLOH_min;
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u32 tRP_min;
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u32 tRR_min;
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u64 tRST_max;
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u32 tWB_max;
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u32 tWC_min;
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u32 tWH_min;
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u32 tWHR_min;
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u32 tWP_min;
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u32 tWW_min;
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};
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#endif
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