448 lines
14 KiB
C
448 lines
14 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fi2c_intr.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:36:38
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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/***************************** Include Files *********************************/
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#include <string.h>
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#include "fio.h"
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#include "ferror_code.h"
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#include "ftypes.h"
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#include "fdebug.h"
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#include "fi2c_hw.h"
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#include "fi2c.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FI2C_DEBUG_TAG "I2C"
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#define FI2C_ERROR(format, ...) FT_DEBUG_PRINT_E(FI2C_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FI2C_INFO(format, ...) FT_DEBUG_PRINT_I(FI2C_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FI2C_DEBUG(format, ...) FT_DEBUG_PRINT_D(FI2C_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/************************** Function Prototypes ******************************/
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static inline void FI2cMasterCallEvtHandler(FI2c *instance_p, u32 evt, void *para)
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{
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FASSERT(instance_p);
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FASSERT(evt < FI2C_MASTER_INTR_EVT_NUM);
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if (instance_p->master_evt_handlers[evt])
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{
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instance_p->master_evt_handlers[evt](instance_p, para);
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}
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}
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static inline void FI2cSlaveCallEvtHandler(FI2c *instance_p, u32 evt, void *para)
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{
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FASSERT(instance_p);
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FASSERT(evt < FI2C_SLAVE_INTR_EVT_NUM);
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FASSERT(para);
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if (instance_p->slave_evt_handlers[evt])
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{
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instance_p->slave_evt_handlers[evt](instance_p, para);
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}
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}
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/**
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* @name: FI2cStubHandler
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* @msg: 主机模式下的I2C中断默认回调函数
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* @return {*}
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* @param {void} *instance_p I2C驱动实例数据
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* @param {void} *param, 中断输入参数
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*/
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static void FI2cStubHandler(void *instance_p, void *param)
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{
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FASSERT(instance_p);
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FI2c *instance = (FI2c *)(instance_p);
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uintptr base_addr = instance->config.base_addr;
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FI2C_INFO("id: %d ,intr cause: 0x%x",
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instance->config.instance_id,
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FI2C_READ_INTR_STAT(base_addr));
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}
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/**
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* @name: FI2cMasterIntrTxEmptyHandler
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* @msg: 主机模式下的I2C TX_FIFO空中断处理函数
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* @return {*}
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* @param {void} *instance_p I2C驱动实例数据
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*/
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static void FI2cMasterIntrTxEmptyHandler(FI2c *instance_p)
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{
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FASSERT(instance_p);
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uintptr base_addr = instance_p->config.base_addr;
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const u8 *buf_p = instance_p->txframe.data_buff;
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u32 intr_mask;
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u32 buf_len;
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u32 reg_val;
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u32 rx_limit, tx_limit;
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buf_len = instance_p->txframe.tx_total_num - instance_p->txframe.tx_cnt;
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rx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_RXFLR_OFFSET);
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tx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_TXFLR_OFFSET);
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while (buf_len > 0 & rx_limit > 0 & tx_limit > 0)
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{
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if (1 == buf_len)
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{
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if (instance_p->status == STATUS_WRITE_IN_PROGRESS)
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{
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reg_val = (FI2C_DATA_MASK & *((u8 *)(instance_p->txframe.data_buff))) |
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FI2C_DATA_CMD_WRITE |
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FI2C_DATA_CMD_STOP;
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instance_p->txframe.data_buff++;
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FI2C_INFO("Write Stop Singal");
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}
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else if (instance_p->status == STATUS_READ_IN_PROGRESS)
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{
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reg_val = FI2C_DATA_CMD_READ | FI2C_DATA_CMD_STOP;
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}
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}
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else
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{
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if (instance_p->status == STATUS_WRITE_IN_PROGRESS)
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{
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reg_val = (FI2C_DATA_MASK & *((u8 *)(instance_p->txframe.data_buff))) |
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FI2C_DATA_CMD_WRITE;
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instance_p->txframe.data_buff++;
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}
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else if (instance_p->status == STATUS_READ_IN_PROGRESS)
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{
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reg_val = FI2C_DATA_CMD_READ;
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}
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}
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FI2C_WRITE_REG32(base_addr, FI2C_DATA_CMD_OFFSET, reg_val);
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rx_limit--;
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tx_limit--;
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buf_len--;
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}
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instance_p->txframe.tx_cnt = instance_p->txframe.tx_total_num - buf_len;
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/*tx over.*/
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if (instance_p->txframe.tx_cnt == instance_p->txframe.tx_total_num)
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{
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instance_p->txframe.tx_cnt = 0;
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if (instance_p->status == STATUS_WRITE_IN_PROGRESS)
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{
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instance_p->status = STATUS_IDLE;
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}
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intr_mask = FI2C_GET_INTRRUPT_MASK(instance_p->config.base_addr);
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intr_mask &= ~(FI2C_INTR_TX_EMPTY);
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FI2C_SET_INTRRUPT_MASK(instance_p->config.base_addr, intr_mask);
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}
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}
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/**
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* @name: FI2cMasterIntrRxFullHandler
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* @msg: 主机模式下的I2C RX_FIFO满处理函数，可通过FI2C_SET_RX_TL(address,level);设置触发level
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* @return {*}
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* @param {void} *instance_p I2C驱动实例数据
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*/
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static void FI2cMasterIntrRxFullHandler(FI2c *instance_p)
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{
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FASSERT(instance_p);
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u32 intr_mask;
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uintptr base_addr = instance_p->config.base_addr;
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u8 emptyfifo = FI2C_READ_REG32(base_addr, FI2C_RXFLR_OFFSET);
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u32 i = 0u;
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u32 reg_val;
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for (i = 0; i < emptyfifo; i++)
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{
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*((u8 *)(instance_p->rxframe.data_buff++)) = FI2C_READ_DATA(base_addr);
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}
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instance_p->rxframe.rx_cnt += emptyfifo;
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if (instance_p->rxframe.rx_cnt >= instance_p->rxframe.rx_total_num)
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{
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instance_p->rxframe.rx_cnt = 0;
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instance_p->status = STATUS_IDLE;
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intr_mask = FI2C_GET_INTRRUPT_MASK(base_addr);
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intr_mask &= ~(FI2C_INTR_RX_FULL);
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FI2C_SET_INTRRUPT_MASK(base_addr, intr_mask);
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FI2cFlushRxFifo(base_addr);
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}
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}
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/**
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* @name: FI2cMasterIntrHandler
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* @msg: 主机模式下的I2C中断响应函数
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* @return {*}
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* @param {s32} vector
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* @param {void} *param, 中断输入参数
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*/
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void FI2cMasterIntrHandler(s32 vector, void *param)
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{
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FASSERT(param);
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FI2c *instance_p = (FI2c *)param;
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uintptr base_addr = instance_p->config.base_addr;
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u32 last_err = 0;
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u32 stat = FI2cClearIntrBits(base_addr, &last_err);
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u32 raw_stat = FI2C_READ_RAW_INTR_STAT(base_addr);
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u32 enabled = FI2C_READ_REG32(base_addr, FI2C_ENABLE_OFFSET);
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u32 val = 0;
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FASSERT(FI2C_MASTER == instance_p->config.work_mode);
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if (!(enabled & FI2C_IC_ENABLE) || !(raw_stat & ~FI2C_INTR_ACTIVITY))
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{
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return;
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}
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if (stat & FI2C_INTR_TX_ABRT) /* trans abort error */
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{
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FI2C_ERROR("last error: 0x%x", last_err);
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FI2C_ERROR("abort source: 0x%x", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
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instance_p->status = STATUS_IDLE;
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FI2C_SET_INTRRUPT_MASK(base_addr, 0); /* disable all intr */
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FI2C_READ_REG32(base_addr, FI2C_CLR_TX_ABRT_OFFSET);
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FI2C_WRITE_REG32(base_addr, FI2C_ENABLE_OFFSET, 1);
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FI2cMasterCallEvtHandler(instance_p, FI2C_EVT_MASTER_TRANS_ABORTED, &val);
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return;
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}
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if (stat & FI2C_INTR_RX_FULL) /* rx complete */
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{
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FI2cMasterIntrRxFullHandler(instance_p);
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FI2cMasterCallEvtHandler(instance_p, FI2C_EVT_MASTER_READ_DONE, &val);
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return;
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}
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if (stat & FI2C_INTR_TX_EMPTY) /* tx complete */
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{
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FI2cMasterIntrTxEmptyHandler(instance_p);
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FI2cMasterCallEvtHandler(instance_p, FI2C_EVT_MASTER_WRITE_DONE, &val);
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return;
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}
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return;
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}
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/**
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* @name: FI2cMasterRegisterIntrHandler
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* @msg: 注册I2C主机中断事件函数
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* @return {*}
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* @param {FI2c} *instance_p I2C驱动实例数据
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* @param {u32} evt 中断事件，参考 FI2C_MASTER_INTR_EVT_NUM
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* @param {FI2cEvtHandler} handler 中断事件回调函数
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*/
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void FI2cMasterRegisterIntrHandler(FI2c *instance_p, u32 evt, FI2cEvtHandler handler)
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{
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FASSERT(instance_p && evt < FI2C_MASTER_INTR_EVT_NUM);
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instance_p->master_evt_handlers[evt] = handler;
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}
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/**
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* @name: FI2cMasterGetIntr
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* @msg: 获取I2C主机的中断
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* @return {u32 } 返回中断寄存器值
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* @param {FI2c} *instance_p I2C驱动实例数据
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*/
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u32 FI2cGetIntr(FI2c *instance_p)
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{
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FASSERT(instance_p);
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FI2cConfig *config_p = &instance_p->config;
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uintptr base_addr = config_p->base_addr;
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FI2C_ERROR("i2c driver not ready");
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return FI2C_ERR_NOT_READY;
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}
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return FI2C_GET_INTRRUPT_MASK(base_addr);
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}
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/**
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* @name: FI2cMasterSetupIntr
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* @msg: 设置I2C主机的中断
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* @return {FError *} 返回错误码
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* @param {FI2c} *instance_p I2C驱动实例数据
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* @param {u32} mask 需要操作的中断寄存器位
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*/
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FError FI2cMasterSetupIntr(FI2c *instance_p, u32 mask)
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{
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FASSERT(instance_p);
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FI2cConfig *config_p = &instance_p->config;
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uintptr base_addr = config_p->base_addr;
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u32 evt;
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FI2C_ERROR("i2c driver not ready");
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return FI2C_ERR_NOT_READY;
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}
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if (FI2C_MASTER != instance_p->config.work_mode)
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{
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FI2C_ERROR("i2c work mode shall be master");
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return FI2C_ERR_INVAL_STATE;
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}
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/* disable all i2c irq */
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FI2C_CLEAR_INTR_STATUS(base_addr);
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for (evt = FI2C_EVT_MASTER_TRANS_ABORTED; evt < FI2C_MASTER_INTR_EVT_NUM; evt++)
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{
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if (instance_p->master_evt_handlers[evt] == NULL)
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{
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FI2cMasterRegisterIntrHandler(instance_p, evt, FI2cStubHandler);
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FI2C_INFO("evt :%d.is default.\r\n", evt);
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}
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}
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FI2C_SET_INTRRUPT_MASK(base_addr, mask);
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return FI2C_SUCCESS;
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}
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/**
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* @name: FI2cSlaveIntrHandler
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* @msg: I2C从机的中断响应函数
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* @return {*}
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* @param {s32} vector
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* @param {void} *param, 输入参数
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*/
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|||
|
|
void FI2cSlaveIntrHandler(s32 vector, void *param)
|
|||
|
|
{
|
|||
|
|
FASSERT(param);
|
|||
|
|
FI2c *instance_p = (FI2c *)param;
|
|||
|
|
uintptr base_addr = instance_p->config.base_addr;
|
|||
|
|
u32 last_err = 0;
|
|||
|
|
|
|||
|
|
u32 stat = FI2C_READ_INTR_STAT(base_addr);
|
|||
|
|
u32 raw_stat = FI2C_READ_RAW_INTR_STAT(base_addr);
|
|||
|
|
u32 enabled = FI2C_READ_REG32(base_addr, FI2C_ENABLE_OFFSET);
|
|||
|
|
boolean slave_active = (FI2C_GET_STATUS(base_addr) & FI2C_STATUS_SLV_ACTIVITY) ? TRUE : FALSE;
|
|||
|
|
u8 val = 0;
|
|||
|
|
u32 reg_val;
|
|||
|
|
|
|||
|
|
FASSERT(FI2C_SLAVE == instance_p->config.work_mode);
|
|||
|
|
|
|||
|
|
if (!(enabled & FI2C_IC_ENABLE) || !(raw_stat & ~FI2C_INTR_ACTIVITY))
|
|||
|
|
{
|
|||
|
|
return;
|
|||
|
|
}
|
|||
|
|
stat = FI2cClearIntrBits(base_addr, &last_err);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_RX_FULL)
|
|||
|
|
{
|
|||
|
|
if (instance_p->status != STATUS_WRITE_IN_PROGRESS)
|
|||
|
|
{
|
|||
|
|
/* code */
|
|||
|
|
instance_p->status = STATUS_WRITE_IN_PROGRESS;
|
|||
|
|
FI2cSlaveCallEvtHandler(instance_p, FI2C_EVT_SLAVE_WRITE_REQUESTED, &val);
|
|||
|
|
}
|
|||
|
|
val = FI2C_READ_DATA(base_addr);
|
|||
|
|
FI2cSlaveCallEvtHandler(instance_p, FI2C_EVT_SLAVE_WRITE_RECEIVED, &val);
|
|||
|
|
}
|
|||
|
|
if (stat & FI2C_INTR_RD_REQ)
|
|||
|
|
{
|
|||
|
|
if (slave_active)
|
|||
|
|
{
|
|||
|
|
FI2C_READ_REG32(base_addr, FI2C_CLR_RD_REQ_OFFSET);
|
|||
|
|
instance_p->status = STATUS_WRITE_IN_PROGRESS;
|
|||
|
|
FI2cSlaveCallEvtHandler(instance_p, FI2C_EVT_SLAVE_READ_REQUESTED, &val);
|
|||
|
|
reg_val = val;
|
|||
|
|
FI2C_WRITE_DATA(base_addr, reg_val);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_RX_DONE)
|
|||
|
|
{
|
|||
|
|
FI2cSlaveCallEvtHandler(instance_p, FI2C_EVT_SLAVE_READ_PROCESSED, &val);
|
|||
|
|
FI2C_READ_REG32(base_addr, FI2C_CLR_RX_DONE_OFFSET);
|
|||
|
|
return;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_STOP_DET)
|
|||
|
|
{
|
|||
|
|
instance_p->status = STATUS_IDLE;
|
|||
|
|
FI2cSlaveCallEvtHandler(instance_p, FI2C_EVT_SLAVE_STOP, &val);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_TX_ABRT) /* trans abort error */
|
|||
|
|
{
|
|||
|
|
FI2C_ERROR("last error: 0x%x", last_err);
|
|||
|
|
FI2C_ERROR("abort source: 0x%x", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FI2cSlaveRegisterIntrHandler
|
|||
|
|
* @msg: 注册I2C从机中断事件函数
|
|||
|
|
* @return {*}
|
|||
|
|
* @param {FI2c} *instance_p I2C驱动实例数据
|
|||
|
|
* @param {u32} evt 中断事件，参考 FI2C_SLAVE_INTR_EVT_NUM
|
|||
|
|
* @param {FI2cEvtHandler} handler 中断事件回调函数
|
|||
|
|
*/
|
|||
|
|
void FI2cSlaveRegisterIntrHandler(FI2c *instance_p, u32 evt, FI2cEvtHandler handler)
|
|||
|
|
{
|
|||
|
|
FASSERT(instance_p && evt < FI2C_SLAVE_INTR_EVT_NUM);
|
|||
|
|
instance_p->slave_evt_handlers[evt] = handler;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FI2cSlaveSetupIntr
|
|||
|
|
* @msg: 设置I2C从机的中断
|
|||
|
|
* @return {FError *} 返回错误码
|
|||
|
|
* @param {FI2c} *instance_p
|
|||
|
|
*/
|
|||
|
|
FError FI2cSlaveSetupIntr(FI2c *instance_p)
|
|||
|
|
{
|
|||
|
|
FASSERT(instance_p);
|
|||
|
|
FI2cConfig *config_p = &instance_p->config;
|
|||
|
|
uintptr base_addr = config_p->base_addr;
|
|||
|
|
u32 evt;
|
|||
|
|
u32 mask;
|
|||
|
|
|
|||
|
|
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
|
|||
|
|
{
|
|||
|
|
FI2C_ERROR("i2c driver not ready");
|
|||
|
|
return FI2C_ERR_NOT_READY;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (FI2C_SLAVE != instance_p->config.work_mode)
|
|||
|
|
{
|
|||
|
|
FI2C_ERROR("i2c work mode shall be slave");
|
|||
|
|
return FI2C_ERR_INVAL_STATE;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* disable all i2c irq */
|
|||
|
|
FI2C_CLEAR_INTR_STATUS(base_addr);
|
|||
|
|
|
|||
|
|
for (evt = FI2C_EVT_SLAVE_READ_REQUESTED; evt < FI2C_SLAVE_INTR_EVT_NUM; evt++)
|
|||
|
|
{
|
|||
|
|
if (instance_p->slave_evt_handlers[evt] == NULL)
|
|||
|
|
{
|
|||
|
|
FI2cSlaveRegisterIntrHandler(instance_p, evt, FI2cStubHandler);
|
|||
|
|
FI2C_INFO("evt :%d.is default.\r\n", evt);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
FI2C_SET_RX_TL(instance_p->config.base_addr, 0);/* 0 表示接收缓冲区大于等于 1 时触发中断 */
|
|||
|
|
FI2C_SET_TX_TL(instance_p->config.base_addr, 0);/* 0 表示发送缓冲区大于等于 1 时触发中断 */
|
|||
|
|
mask = FI2C_GET_INTRRUPT_MASK(base_addr);
|
|||
|
|
mask |= (FI2C_INTR_SLAVE_DEF_MASK);
|
|||
|
|
FI2C_SET_INTRRUPT_MASK(base_addr, mask);
|
|||
|
|
|
|||
|
|
return FI2C_SUCCESS;
|
|||
|
|
}
|