428 lines
14 KiB
C
428 lines
14 KiB
C
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/****************************************************************************
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* csky/hardware/bsp/common/ethernet_enc28j60/ethernet_enc28j60.h
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*
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* Copyright (C) 2016 The YunOS Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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****************************************************************************/
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#ifndef _ETHERNET_ENC28J60_H__
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#define _ETHERNET_ENC28J60_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/* ****** ETH ****** */
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#define ETH_HEADER_LEN 14
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/* values of certain bytes: */
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#define ETHTYPE_ARP_H_V 0x08
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#define ETHTYPE_ARP_L_V 0x06
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#define ETHTYPE_IP_H_V 0x08
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#define ETHTYPE_IP_L_V 0x00
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/* byte positions in the ethernet frame:
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Ethernet type field (2bytes): */
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#define ETH_TYPE_H_P 12
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#define ETH_TYPE_L_P 13
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#define ETH_DST_MAC 0
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#define ETH_SRC_MAC 6
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/* ******* ARP ******* */
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#define ETH_ARP_OPCODE_REPLY_H_V 0x0
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#define ETH_ARP_OPCODE_REPLY_L_V 0x02
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#define ETHTYPE_ARP_L_V 0x06
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/* arp.dst.ip */
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#define ETH_ARP_DST_IP_P 0x26
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/* arp.opcode */
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#define ETH_ARP_OPCODE_H_P 0x14
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#define ETH_ARP_OPCODE_L_P 0x15
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/* arp.src.mac */
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#define ETH_ARP_SRC_MAC_P 0x16
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#define ETH_ARP_SRC_IP_P 0x1c
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#define ETH_ARP_DST_MAC_P 0x20
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#define ETH_ARP_DST_IP_P 0x26
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/* ******* IP ******* */
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#define IP_HEADER_LEN 20
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/* ip.src */
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#define IP_SRC_P 0x1a
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#define IP_DST_P 0x1e
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#define IP_HEADER_LEN_VER_P 0xe
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#define IP_CHECKSUM_P 0x18
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#define IP_TTL_P 0x16
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#define IP_FLAGS_P 0x14
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#define IP_P 0xe
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#define IP_TOTLEN_H_P 0x10
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#define IP_TOTLEN_L_P 0x11
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#define IP_PROTO_P 0x17
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#define IP_PROTO_ICMP_V 1
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#define IP_PROTO_TCP_V 6
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/* 17=0x11 */
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#define IP_PROTO_UDP_V 17
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/* ******* ICMP ******* */
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#define ICMP_TYPE_ECHOREPLY_V 0
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#define ICMP_TYPE_ECHOREQUEST_V 8
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#define ICMP_TYPE_P 0x22
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#define ICMP_CHECKSUM_P 0x24
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/* ******* UDP ******* */
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#define UDP_HEADER_LEN 8
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#define UDP_SRC_PORT_H_P 0x22
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#define UDP_SRC_PORT_L_P 0x23
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#define UDP_DST_PORT_H_P 0x24
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#define UDP_DST_PORT_L_P 0x25
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#define UDP_LEN_H_P 0x26
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#define UDP_LEN_L_P 0x27
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#define UDP_CHECKSUM_H_P 0x28
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#define UDP_CHECKSUM_L_P 0x29
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#define UDP_DATA_P 0x2a
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/* ******* TCP ******* */
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#define TCP_SRC_PORT_H_P 0x22
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#define TCP_SRC_PORT_L_P 0x23
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#define TCP_DST_PORT_H_P 0x24
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#define TCP_DST_PORT_L_P 0x25
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/* the tcp seq number is 4 bytes 0x26-0x29 */
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#define TCP_SEQ_H_P 0x26
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#define TCP_SEQACK_H_P 0x2a
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/* flags: SYN=2 */
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#define TCP_FLAGS_P 0x2f
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#define TCP_FLAGS_SYN_V 2
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#define TCP_FLAGS_FIN_V 1
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#define TCP_FLAGS_PUSH_V 8
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#define TCP_FLAGS_SYNACK_V 0x12
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#define TCP_FLAGS_ACK_V 0x10
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#define TCP_FLAGS_PSHACK_V 0x18
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/* plain len without the options: */
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#define TCP_HEADER_LEN_PLAIN 20
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#define TCP_HEADER_LEN_P 0x2e
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#define TCP_CHECKSUM_H_P 0x32
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#define TCP_CHECKSUM_L_P 0x33
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#define TCP_OPTIONS_P 0x36
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/* ENC28J60 Control Registers
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Control register definitions are a combination of address,
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bank number, and Ethernet/MAC/PHY indicator bits.
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- Register address (bits 0-4)
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- Bank number (bits 5-6)
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- MAC/PHY indicator (bit 7) */
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#define ADDR_MASK 0x1F
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#define BANK_MASK 0x60
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#define SPRD_MASK 0x80
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/* All-bank registers */
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#define EIE 0x1B
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#define EIR 0x1C
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#define ESTAT 0x1D
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#define ECON2 0x1E
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#define ECON1 0x1F
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/* Bank 0 registers */
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#define ERDPTL (0x00|0x00)
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#define ERDPTH (0x01|0x00)
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#define EWRPTL (0x02|0x00)
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#define EWRPTH (0x03|0x00)
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#define ETXSTL (0x04|0x00)
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#define ETXSTH (0x05|0x00)
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#define ETXNDL (0x06|0x00)
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#define ETXNDH (0x07|0x00)
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#define ERXSTL (0x08|0x00)
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#define ERXSTH (0x09|0x00)
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#define ERXNDL (0x0A|0x00)
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#define ERXNDH (0x0B|0x00)
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#define ERXRDPTL (0x0C|0x00)
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#define ERXRDPTH (0x0D|0x00)
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#define ERXWRPTL (0x0E|0x00)
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#define ERXWRPTH (0x0F|0x00)
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#define EDMASTL (0x10|0x00)
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#define EDMASTH (0x11|0x00)
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#define EDMANDL (0x12|0x00)
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#define EDMANDH (0x13|0x00)
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#define EDMADSTL (0x14|0x00)
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#define EDMADSTH (0x15|0x00)
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#define EDMACSL (0x16|0x00)
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#define EDMACSH (0x17|0x00)
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/* Bank 1 registers */
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#define EHT0 (0x00|0x20)
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#define EHT1 (0x01|0x20)
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#define EHT2 (0x02|0x20)
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#define EHT3 (0x03|0x20)
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#define EHT4 (0x04|0x20)
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#define EHT5 (0x05|0x20)
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#define EHT6 (0x06|0x20)
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#define EHT7 (0x07|0x20)
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#define EPMM0 (0x08|0x20)
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#define EPMM1 (0x09|0x20)
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#define EPMM2 (0x0A|0x20)
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#define EPMM3 (0x0B|0x20)
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#define EPMM4 (0x0C|0x20)
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#define EPMM5 (0x0D|0x20)
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#define EPMM6 (0x0E|0x20)
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#define EPMM7 (0x0F|0x20)
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#define EPMCSL (0x10|0x20)
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#define EPMCSH (0x11|0x20)
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#define EPMOL (0x14|0x20)
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#define EPMOH (0x15|0x20)
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#define EWOLIE (0x16|0x20)
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#define EWOLIR (0x17|0x20)
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#define ERXFCON (0x18|0x20)
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#define EPKTCNT (0x19|0x20)
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/* Bank 2 registers */
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#define MACON1 (0x00|0x40|0x80)
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#define MACON2 (0x01|0x40|0x80)
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#define MACON3 (0x02|0x40|0x80)
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#define MACON4 (0x03|0x40|0x80)
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#define MABBIPG (0x04|0x40|0x80)
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#define MAIPGL (0x06|0x40|0x80)
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#define MAIPGH (0x07|0x40|0x80)
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#define MACLCON1 (0x08|0x40|0x80)
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#define MACLCON2 (0x09|0x40|0x80)
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#define MAMXFLL (0x0A|0x40|0x80)
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#define MAMXFLH (0x0B|0x40|0x80)
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#define MAPHSUP (0x0D|0x40|0x80)
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#define MICON (0x11|0x40|0x80)
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#define MICMD (0x12|0x40|0x80)
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#define MIREGADR (0x14|0x40|0x80)
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#define MIWRL (0x16|0x40|0x80)
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#define MIWRH (0x17|0x40|0x80)
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#define MIRDL (0x18|0x40|0x80)
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#define MIRDH (0x19|0x40|0x80)
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/* Bank 3 registers */
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#define MAADR1 (0x00|0x60|0x80)
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#define MAADR0 (0x01|0x60|0x80)
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#define MAADR3 (0x02|0x60|0x80)
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#define MAADR2 (0x03|0x60|0x80)
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#define MAADR5 (0x04|0x60|0x80)
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#define MAADR4 (0x05|0x60|0x80)
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#define EBSTSD (0x06|0x60)
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#define EBSTCON (0x07|0x60)
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#define EBSTCSL (0x08|0x60)
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#define EBSTCSH (0x09|0x60)
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#define MISTAT (0x0A|0x60|0x80)
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#define EREVID (0x12|0x60)
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#define ECOCON (0x15|0x60)
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#define EFLOCON (0x17|0x60)
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#define EPAUSL (0x18|0x60)
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#define EPAUSH (0x19|0x60)
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/* PHY registers */
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHHID1 0x02
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#define PHHID2 0x03
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#define PHCON2 0x10
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#define PHSTAT2 0x11
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#define PHIE 0x12
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#define PHIR 0x13
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#define PHLCON 0x14
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/* ENC28J60 ERXFCON Register Bit Definitions */
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#define ERXFCON_UCEN 0x80
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#define ERXFCON_ANDOR 0x40
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#define ERXFCON_CRCEN 0x20
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#define ERXFCON_PMEN 0x10
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#define ERXFCON_MPEN 0x08
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#define ERXFCON_HTEN 0x04
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#define ERXFCON_MCEN 0x02
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#define ERXFCON_BCEN 0x01
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/* ENC28J60 EIE Register Bit Definitions */
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#define EIE_INTIE 0x80
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#define EIE_PKTIE 0x40
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#define EIE_DMAIE 0x20
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#define EIE_LINKIE 0x10
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#define EIE_TXIE 0x08
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#define EIE_WOLIE 0x04
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#define EIE_TXERIE 0x02
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#define EIE_RXERIE 0x01
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#define EIE_ALLCLOSE 0xff
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/* ENC28J60 EIR Register Bit Definitions */
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#define EIR_PKTIF 0x40
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#define EIR_DMAIF 0x20
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#define EIR_LINKIF 0x10
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#define EIR_TXIF 0x08
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#define EIR_WOLIF 0x04
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#define EIR_TXERIF 0x02
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#define EIR_RXERIF 0x01
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#define EIR_ALLINTS 0x7b /* All interrupts */
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/* ENC28J60 ESTAT Register Bit Definitions */
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#define ESTAT_INT 0x80
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#define ESTAT_LATECOL 0x10
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#define ESTAT_RXBUSY 0x04
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#define ESTAT_TXABRT 0x02
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#define ESTAT_CLKRDY 0x01
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/* ENC28J60 ECON2 Register Bit Definitions */
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#define ECON2_AUTOINC 0x80
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#define ECON2_PKTDEC 0x40
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#define ECON2_PWRSV 0x20
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#define ECON2_VRPS 0x08
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/* ENC28J60 ECON1 Register Bit Definitions */
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#define ECON1_TXRST 0x80
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#define ECON1_RXRST 0x40
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#define ECON1_DMAST 0x20
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#define ECON1_CSUMEN 0x10
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#define ECON1_TXRTS 0x08
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#define ECON1_RXEN 0x04
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#define ECON1_BSEL1 0x02
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#define ECON1_BSEL0 0x01
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/* ENC28J60 MACON1 Register Bit Definitions */
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#define MACON1_LOOPBK 0x10
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#define MACON1_TXPAUS 0x08
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#define MACON1_RXPAUS 0x04
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#define MACON1_PASSALL 0x02
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#define MACON1_MARXEN 0x01
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/* ENC28J60 MACON2 Register Bit Definitions */
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#define MACON2_MARST 0x80
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#define MACON2_RNDRST 0x40
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#define MACON2_MARXRST 0x08
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#define MACON2_RFUNRST 0x04
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#define MACON2_MATXRST 0x02
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#define MACON2_TFUNRST 0x01
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/* ENC28J60 MACON3 Register Bit Definitions */
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#define MACON3_PADCFG2 0x80
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#define MACON3_PADCFG1 0x40
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#define MACON3_PADCFG0 0x20
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#define MACON3_TXCRCEN 0x10
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#define MACON3_PHDRLEN 0x08
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#define MACON3_HFRMLEN 0x04
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#define MACON3_FRMLNEN 0x02
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#define MACON3_FULDPX 0x01
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/* ENC28J60 MICMD Register Bit Definitions */
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#define MICMD_MIISCAN 0x02
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#define MICMD_MIIRD 0x01
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/* ENC28J60 MISTAT Register Bit Definitions */
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#define MISTAT_NVALID 0x04
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#define MISTAT_SCAN 0x02
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#define MISTAT_BUSY 0x01
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/* ENC28J60 PHY PHCON1 Register Bit Definitions */
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#define PHCON1_PRST 0x8000
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#define PHCON1_PLOOPBK 0x4000
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#define PHCON1_PPWRSV 0x0800
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#define PHCON1_PDPXMD 0x0100
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/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
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#define PHSTAT1_PFDPX 0x1000
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#define PHSTAT1_PHDPX 0x0800
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#define PHSTAT1_LLSTAT 0x0004
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#define PHSTAT1_JBSTAT 0x0002
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/* ENC28J60 PHY PHCON2 Register Bit Definitions */
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#define PHCON2_FRCLINK 0x4000
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#define PHCON2_TXDIS 0x2000
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#define PHCON2_JABBER 0x0400
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#define PHCON2_HDLDIS 0x0100
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/* ENC28J60 PHY PHIE Register Bit Definitions */
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#define PHIE_PLNKIE 0x0010
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#define PHIE_PGEIE 0x0002
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/* ENC28J60 Packet Control Byte Bit Definitions */
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#define PKTCTRL_PHUGEEN 0x08
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#define PKTCTRL_PPADEN 0x04
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#define PKTCTRL_PCRCEN 0x02
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#define PKTCTRL_POVERRIDE 0x01
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/* SPI operation codes */
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#define ENC28J60_READ_CTRL_REG 0x00
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#define ENC28J60_READ_BUF_MEM 0x3A
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#define ENC28J60_WRITE_CTRL_REG 0x40
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#define ENC28J60_WRITE_BUF_MEM 0x7A
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#define ENC28J60_BIT_FIELD_SET 0x80
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#define ENC28J60_BIT_FIELD_CLR 0xA0
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#define ENC28J60_SOFT_RESET 0xFF
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/* The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
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buffer boundaries applied to internal 8K ram
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the entire available packet buffer space is allocated
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start with recbuf at 0/ */
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#define RXSTART_INIT 0x0
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/* receive buffer end */
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#define RXSTOP_INIT (0x1FFF-0x0600-1)
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/* start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes) */
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#define TXSTART_INIT (0x1FFF-0x0600)
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/* stp TX buffer at end of mem */
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#define TXSTOP_INIT 0x1FFF
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/* max frame length which the conroller will accept: */
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#define MAX_FRAMELEN 1518 /* (note: maximum ethernet frame length would be 1518) */
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void enc28j60_spi_cs_status_change(int status);
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#if 1//defined CONFIG_PHOBOS_GENERAL
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#define PA5_A8 15
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#define PA1 12
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#define ENC28J60_CSL() enc28j60_spi_cs_status_change(0); //yunos_bsp_gpio_set_value(20, GPIO_VALUE_LOW); /* SPI_CS_LOW */
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#define ENC28J60_CSH() enc28j60_spi_cs_status_change(1); //yunos_bsp_gpio_set_value(20, GPIO_VALUE_HIGH); /* SPI_CS_HIGH */
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#else
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#define PA5_A8 47
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#define ENC28J60_CSL() enc28j60_spi_cs_status_change(0); //yunos_bsp_gpio_set_value(44, GPIO_VALUE_LOW); /* SPI_CS_LOW */
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#define ENC28J60_CSH() enc28j60_spi_cs_status_change(1); //yunos_bsp_gpio_set_value(44, GPIO_VALUE_HIGH); /* SPI_CS_HIGH */
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#endif
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typedef struct _spi_net_ops_t {
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int (*init)(const uint8_t *macaddr);
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int (*recv)(uint8_t *, uint16_t);
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int (*send)(uint8_t *, uint16_t);
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int (*reset)(void);
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int (*irq_enable)(int);
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int (*set_macaddr)(const uint8_t *macaddr);
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int (*get_link_status)(void);
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} net_ops_t;
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enum enc28j60_reset {
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RST_ENC28J60_ALL,
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RST_ENC28J60_TX,
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RST_ENC28J60_RX
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};
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int yunos_bsp_enc28j60_init(const uint8_t *macaddr);
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int yunos_bsp_enc28j60_reset(void);
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int yunos_bsp_enc28j60_get_link_status(void);
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int yunos_bsp_enc28j60_set_irq_enable(int enable);
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int yunos_bsp_enc28j60_get_interrupt_status(void);
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int yunos_bsp_enc28j60_set_interrupt_status(int status);
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||
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//int yunos_bsp_enc28j60_set_interrupt(gpio_interrupt_t interrupt_cb);
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int yunos_bsp_enc28j60_get_pkt_cnt(void);
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||
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int yunos_bsp_enc28j60_net_init(void);
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||
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int yunos_bsp_enc28j60_set_macaddr(const uint8_t *macaddr);
|
||
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net_ops_t *yunos_bsp_spi_net_get_ctrl_ops(void);
|
||
|
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int yunos_bsp_enc28j60_handle_int_error(int status);
|
||
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|
||
|
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int yunos_bsp_enc28j60_send_start(uint16_t len);
|
||
|
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void yunos_bsp_enc28j60_send_data(uint8_t *packet, uint16_t len);
|
||
|
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void yunos_bsp_enc28j60_send_end(void);
|
||
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|
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|
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int yunos_bsp_enc28j60_recv_start(uint16_t maxlen);
|
||
|
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int yunos_bsp_enc28j60_recv_data(uint8_t *packet, uint16_t len);
|
||
|
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void yunos_bsp_enc28j60_recv_end(void);
|
||
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|
||
|
|
void yunos_bsp_enc28j60_hard_reset(void);
|
||
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|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
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|
||
|
|
#endif /* _ETHERNET_ENC28J60_H__ */
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