542 lines
16 KiB
C
542 lines
16 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_pint.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.pint"
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Irq number array */
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static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
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/*! @brief Callback function array for PINT(s). */
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static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
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/*******************************************************************************
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* Code
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******************************************************************************/
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void PINT_Init(PINT_Type *base)
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{
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uint32_t i;
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uint32_t pmcfg;
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assert(base);
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pmcfg = 0;
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for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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{
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s_pintCallback[i] = NULL;
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}
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/* Disable all bit slices */
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for (i = 0; i < PINT_PIN_INT_COUNT; i++)
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{
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pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
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}
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#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
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/* Enable the peripheral clock */
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CLOCK_EnableClock(kCLOCK_GpioInt);
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/* Reset the peripheral */
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RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
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#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
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/* Enable the peripheral clock */
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CLOCK_EnableClock(kCLOCK_Gpio0);
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/* Reset the peripheral */
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RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
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#else
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/* Enable the peripheral clock */
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CLOCK_EnableClock(kCLOCK_Pint);
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/* Reset the peripheral */
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RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
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#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/
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/* Disable all pattern match bit slices */
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base->PMCFG = pmcfg;
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}
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void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
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{
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assert(base);
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/* Clear Rise and Fall flags first */
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PINT_PinInterruptClrRiseFlag(base, intr);
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PINT_PinInterruptClrFallFlag(base, intr);
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/* select level or edge sensitive */
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base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U);
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/* enable rising or level interrupt */
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if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
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{
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base->SIENR = 1U << intr;
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}
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else
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{
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base->CIENR = 1U << intr;
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}
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/* Enable falling or select high level */
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if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
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{
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base->SIENF = 1U << intr;
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}
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else
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{
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base->CIENF = 1U << intr;
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}
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s_pintCallback[intr] = callback;
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}
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void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
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{
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uint32_t mask;
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bool level;
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assert(base);
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*enable = kPINT_PinIntEnableNone;
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level = false;
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mask = 1U << pintr;
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if (base->ISEL & mask)
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{
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/* Pin interrupt is level sensitive */
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level = true;
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}
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if (base->IENR & mask)
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{
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if (level)
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{
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/* Level interrupt is enabled */
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*enable = kPINT_PinIntEnableLowLevel;
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}
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else
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{
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/* Rising edge interrupt */
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*enable = kPINT_PinIntEnableRiseEdge;
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}
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}
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if (base->IENF & mask)
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{
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if (level)
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{
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/* Level interrupt is active high */
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*enable = kPINT_PinIntEnableHighLevel;
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}
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else
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{
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/* Either falling or both edge */
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if (*enable == kPINT_PinIntEnableRiseEdge)
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{
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/* Rising and faling edge */
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*enable = kPINT_PinIntEnableBothEdges;
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}
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else
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{
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/* Falling edge */
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*enable = kPINT_PinIntEnableFallEdge;
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}
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}
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}
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*callback = s_pintCallback[pintr];
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}
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void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
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{
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uint32_t src_shift;
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uint32_t cfg_shift;
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uint32_t pmcfg;
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assert(base);
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src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
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cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
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/* Input source selection for selected bit slice */
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base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift);
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/* Bit slice configuration */
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pmcfg = base->PMCFG;
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pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
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/* If end point is true, enable the bits */
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if (bslice != 7U)
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{
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if (cfg->end_point)
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{
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pmcfg |= (0x1U << bslice);
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}
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else
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{
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pmcfg &= ~(0x1U << bslice);
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}
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}
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base->PMCFG = pmcfg;
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/* Save callback pointer */
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s_pintCallback[bslice] = cfg->callback;
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}
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void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
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{
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uint32_t src_shift;
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uint32_t cfg_shift;
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assert(base);
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src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
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cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
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cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift);
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cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift);
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if (bslice == 7U)
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{
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cfg->end_point = true;
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}
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else
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{
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cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice;
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}
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cfg->callback = s_pintCallback[bslice];
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}
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uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
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{
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uint32_t pmctrl;
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uint32_t pmstatus;
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uint32_t pmsrc;
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pmctrl = PINT->PMCTRL;
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pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
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if (pmstatus)
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{
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/* Reset Pattern match engine detection logic */
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pmsrc = base->PMSRC;
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base->PMSRC = pmsrc;
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}
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return (pmstatus);
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}
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void PINT_EnableCallback(PINT_Type *base)
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{
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uint32_t i;
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assert(base);
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PINT_PinInterruptClrStatusAll(base);
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for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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{
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NVIC_ClearPendingIRQ(s_pintIRQ[i]);
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PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
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EnableIRQ(s_pintIRQ[i]);
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}
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}
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void PINT_DisableCallback(PINT_Type *base)
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{
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uint32_t i;
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assert(base);
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for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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{
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DisableIRQ(s_pintIRQ[i]);
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PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
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NVIC_ClearPendingIRQ(s_pintIRQ[i]);
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}
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}
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void PINT_Deinit(PINT_Type *base)
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{
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uint32_t i;
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assert(base);
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/* Cleanup */
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PINT_DisableCallback(base);
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for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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{
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s_pintCallback[i] = NULL;
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}
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#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
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/* Reset the peripheral */
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RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
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/* Disable the peripheral clock */
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CLOCK_DisableClock(kCLOCK_GpioInt);
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#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
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/* Reset the peripheral */
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RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
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/* Disable the peripheral clock */
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CLOCK_DisableClock(kCLOCK_Gpio0);
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#else
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/* Reset the peripheral */
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RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
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/* Disable the peripheral clock */
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CLOCK_DisableClock(kCLOCK_Pint);
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#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
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}
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/* IRQ handler functions overloading weak symbols in the startup */
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void PIN_INT0_DriverIRQHandler(void)
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{
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uint32_t pmstatus;
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/* Reset pattern match detection */
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pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
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/* Call user function */
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if (s_pintCallback[kPINT_PinInt0] != NULL)
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{
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s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
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}
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if((PINT->ISEL & 0x1U) == 0x0U)
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{
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/* Edge sensitive: clear Pin interrupt after callback */
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PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
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void PIN_INT1_DriverIRQHandler(void)
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{
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uint32_t pmstatus;
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/* Reset pattern match detection */
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pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
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/* Call user function */
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if (s_pintCallback[kPINT_PinInt1] != NULL)
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{
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s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
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}
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if((PINT->ISEL & 0x2U) == 0x0U)
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{
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/* Edge sensitive: clear Pin interrupt after callback */
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PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
|
||
|
|
void PIN_INT2_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
uint32_t pmstatus;
|
||
|
|
|
||
|
|
/* Reset pattern match detection */
|
||
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||
|
|
/* Call user function */
|
||
|
|
if (s_pintCallback[kPINT_PinInt2] != NULL)
|
||
|
|
{
|
||
|
|
s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
|
||
|
|
}
|
||
|
|
if((PINT->ISEL & 0x4U) == 0x0U)
|
||
|
|
{
|
||
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
||
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
|
||
|
|
void PIN_INT3_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
uint32_t pmstatus;
|
||
|
|
|
||
|
|
/* Reset pattern match detection */
|
||
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||
|
|
/* Call user function */
|
||
|
|
if (s_pintCallback[kPINT_PinInt3] != NULL)
|
||
|
|
{
|
||
|
|
s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
|
||
|
|
}
|
||
|
|
if((PINT->ISEL & 0x8U) == 0x0U)
|
||
|
|
{
|
||
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
||
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
|
||
|
|
void PIN_INT4_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
uint32_t pmstatus;
|
||
|
|
|
||
|
|
/* Reset pattern match detection */
|
||
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||
|
|
/* Call user function */
|
||
|
|
if (s_pintCallback[kPINT_PinInt4] != NULL)
|
||
|
|
{
|
||
|
|
s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
|
||
|
|
}
|
||
|
|
if((PINT->ISEL & 0x10U) == 0x0U)
|
||
|
|
{
|
||
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
||
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
|
||
|
|
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
||
|
|
void PIN_INT5_DAC1_IRQHandler(void)
|
||
|
|
#else
|
||
|
|
void PIN_INT5_DriverIRQHandler(void)
|
||
|
|
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
||
|
|
{
|
||
|
|
uint32_t pmstatus;
|
||
|
|
|
||
|
|
/* Reset pattern match detection */
|
||
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||
|
|
/* Call user function */
|
||
|
|
if (s_pintCallback[kPINT_PinInt5] != NULL)
|
||
|
|
{
|
||
|
|
s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
|
||
|
|
}
|
||
|
|
if((PINT->ISEL & 0x20U) == 0x0U)
|
||
|
|
{
|
||
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
||
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
|
||
|
|
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
||
|
|
void PIN_INT6_USART3_IRQHandler(void)
|
||
|
|
#else
|
||
|
|
void PIN_INT6_DriverIRQHandler(void)
|
||
|
|
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
||
|
|
{
|
||
|
|
uint32_t pmstatus;
|
||
|
|
|
||
|
|
/* Reset pattern match detection */
|
||
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||
|
|
/* Call user function */
|
||
|
|
if (s_pintCallback[kPINT_PinInt6] != NULL)
|
||
|
|
{
|
||
|
|
s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
|
||
|
|
}
|
||
|
|
if((PINT->ISEL & 0x40U) == 0x0U)
|
||
|
|
{
|
||
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
||
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
|
||
|
|
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
||
|
|
void PIN_INT7_USART4_IRQHandler(void)
|
||
|
|
#else
|
||
|
|
void PIN_INT7_DriverIRQHandler(void)
|
||
|
|
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
||
|
|
{
|
||
|
|
uint32_t pmstatus;
|
||
|
|
|
||
|
|
/* Reset pattern match detection */
|
||
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||
|
|
/* Call user function */
|
||
|
|
if (s_pintCallback[kPINT_PinInt7] != NULL)
|
||
|
|
{
|
||
|
|
s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
|
||
|
|
}
|
||
|
|
if((PINT->ISEL & 0x80U) == 0x0U)
|
||
|
|
{
|
||
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
||
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|