450 lines
15 KiB
C
450 lines
15 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_ctimer.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.ctimer"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address
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*
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* @param base Ctimer peripheral base address
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*
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* @return The Timer instance
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*/
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static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to Timer bases for each instance. */
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static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to Timer clocks for each instance. */
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static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET
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/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */
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static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N;
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#else
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/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */
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static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
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#endif
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/*! @brief Pointers real ISRs installed by drivers for each instance. */
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static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
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/*! @brief Callback type installed by drivers for each instance. */
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static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
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/*! @brief Array to map timer instance to IRQ number. */
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static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
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{
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uint32_t instance;
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uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ctimerArrayCount; instance++)
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{
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if (s_ctimerBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ctimerArrayCount);
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return instance;
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}
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void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
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{
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assert(config);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the timer clock*/
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CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset the module */
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RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
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/* Setup the cimer mode and count select */
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base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
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/* Setup the timer prescale value */
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base->PR = CTIMER_PR_PRVAL(config->prescale);
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}
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void CTIMER_Deinit(CTIMER_Type *base)
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{
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uint32_t index = CTIMER_GetInstance(base);
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/* Stop the timer */
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base->TCR &= ~CTIMER_TCR_CEN_MASK;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the timer clock*/
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CLOCK_DisableClock(s_ctimerClocks[index]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Disable IRQ at NVIC Level */
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DisableIRQ(s_ctimerIRQ[index]);
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}
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void CTIMER_GetDefaultConfig(ctimer_config_t *config)
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{
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assert(config);
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/* Run as a timer */
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config->mode = kCTIMER_TimerMode;
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/* This field is ignored when mode is timer */
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config->input = kCTIMER_Capture_0;
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/* Timer counter is incremented on every APB bus clock */
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config->prescale = 0;
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}
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status_t CTIMER_SetupPwm(CTIMER_Type *base,
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ctimer_match_t matchChannel,
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uint8_t dutyCyclePercent,
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uint32_t pwmFreq_Hz,
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uint32_t srcClock_Hz,
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bool enableInt)
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{
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assert(pwmFreq_Hz > 0);
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uint32_t reg;
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uint32_t period, pulsePeriod = 0;
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uint32_t timerClock = srcClock_Hz / (base->PR + 1);
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uint32_t index = CTIMER_GetInstance(base);
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if (matchChannel == kCTIMER_Match_3)
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{
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return kStatus_Fail;
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}
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/* Enable PWM mode on the channel */
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base->PWMC |= (1U << matchChannel);
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/* Clear the stop, reset and interrupt bits for this channel */
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reg = base->MCR;
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reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
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/* If call back function is valid then enable match interrupt for the channel */
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if (enableInt)
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{
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reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
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}
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/* Reset the counter when match on channel 3 */
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reg |= CTIMER_MCR_MR3R_MASK;
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base->MCR = reg;
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/* Calculate PWM period match value */
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period = (timerClock / pwmFreq_Hz) - 1;
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/* Calculate pulse width match value */
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if (dutyCyclePercent == 0)
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{
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pulsePeriod = period + 1;
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}
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else
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{
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pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
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}
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/* Match on channel 3 will define the PWM period */
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base->MR[kCTIMER_Match_3] = period;
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/* This will define the PWM pulse period */
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base->MR[matchChannel] = pulsePeriod;
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/* Clear status flags */
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CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
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/* If call back function is valid then enable interrupt and update the call back function */
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if (enableInt)
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{
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EnableIRQ(s_ctimerIRQ[index]);
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}
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return kStatus_Success;
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}
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status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base,
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ctimer_match_t matchChannel,
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uint32_t pwmPeriod,
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uint32_t pulsePeriod,
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bool enableInt)
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{
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uint32_t reg;
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uint32_t index = CTIMER_GetInstance(base);
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if (matchChannel == kCTIMER_Match_3)
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{
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return kStatus_Fail;
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}
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/* Enable PWM mode on the channel */
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base->PWMC |= (1U << matchChannel);
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/* Clear the stop, reset and interrupt bits for this channel */
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reg = base->MCR;
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reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
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/* If call back function is valid then enable match interrupt for the channel */
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if (enableInt)
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{
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reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
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}
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/* Reset the counter when match on channel 3 */
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reg |= CTIMER_MCR_MR3R_MASK;
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base->MCR = reg;
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/* Match on channel 3 will define the PWM period */
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base->MR[kCTIMER_Match_3] = pwmPeriod;
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/* This will define the PWM pulse period */
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base->MR[matchChannel] = pulsePeriod;
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/* Clear status flags */
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CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
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/* If call back function is valid then enable interrupt and update the call back function */
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if (enableInt)
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{
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EnableIRQ(s_ctimerIRQ[index]);
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}
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return kStatus_Success;
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}
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void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
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{
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uint32_t pulsePeriod = 0, period;
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/* Match channel 3 defines the PWM period */
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period = base->MR[kCTIMER_Match_3];
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/* Calculate pulse width match value */
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pulsePeriod = (period * dutyCyclePercent) / 100;
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/* For 0% dutycyle, make pulse period greater than period so the event will never occur */
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if (dutyCyclePercent == 0)
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{
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pulsePeriod = period + 1;
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}
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else
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{
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pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
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}
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/* Update dutycycle */
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base->MR[matchChannel] = pulsePeriod;
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}
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void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
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{
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uint32_t reg;
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uint32_t index = CTIMER_GetInstance(base);
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/* Set the counter operation when a match on this channel occurs */
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reg = base->MCR;
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reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
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reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
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reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
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reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
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base->MCR = reg;
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reg = base->EMR;
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/* Set the match output operation when a match on this channel occurs */
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reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
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reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
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/* Set the initial state of the EM bit/output */
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reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
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reg |= (uint32_t)config->outPinInitState << matchChannel;
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base->EMR = reg;
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/* Set the match value */
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base->MR[matchChannel] = config->matchValue;
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/* Clear status flags */
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CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
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/* If interrupt is enabled then enable interrupt and update the call back function */
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if (config->enableInterrupt)
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{
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EnableIRQ(s_ctimerIRQ[index]);
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}
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}
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void CTIMER_SetupCapture(CTIMER_Type *base,
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ctimer_capture_channel_t capture,
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ctimer_capture_edge_t edge,
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bool enableInt)
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{
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uint32_t reg = base->CCR;
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uint32_t index = CTIMER_GetInstance(base);
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/* Set the capture edge */
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reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
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reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
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/* Clear status flags */
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CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
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/* If call back function is valid then enable capture interrupt for the channel and update the call back function */
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if (enableInt)
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{
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reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
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EnableIRQ(s_ctimerIRQ[index]);
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}
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base->CCR = reg;
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}
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void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
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{
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uint32_t index = CTIMER_GetInstance(base);
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s_ctimerCallback[index] = cb_func;
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ctimerCallbackType[index] = cb_type;
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}
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void CTIMER_GenericIRQHandler(uint32_t index)
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|
|
{
|
||
|
|
uint32_t int_stat, i, mask;
|
||
|
|
/* Get Interrupt status flags */
|
||
|
|
int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
|
||
|
|
/* Clear the status flags that were set */
|
||
|
|
CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
|
||
|
|
if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
|
||
|
|
{
|
||
|
|
if (s_ctimerCallback[index][0])
|
||
|
|
{
|
||
|
|
s_ctimerCallback[index][0](int_stat);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
|
||
|
|
for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
|
||
|
|
#else
|
||
|
|
for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++)
|
||
|
|
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
||
|
|
{
|
||
|
|
mask = 0x01 << i;
|
||
|
|
/* For each status flag bit that was set call the callback function if it is valid */
|
||
|
|
if ((int_stat & mask) && (s_ctimerCallback[index][i]))
|
||
|
|
{
|
||
|
|
s_ctimerCallback[index][i](int_stat);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/* IRQ handler functions overloading weak symbols in the startup */
|
||
|
|
#if defined(CTIMER0)
|
||
|
|
void CTIMER0_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
CTIMER_GenericIRQHandler(0);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CTIMER1)
|
||
|
|
void CTIMER1_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
CTIMER_GenericIRQHandler(1);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CTIMER2)
|
||
|
|
void CTIMER2_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
CTIMER_GenericIRQHandler(2);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CTIMER3)
|
||
|
|
void CTIMER3_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
CTIMER_GenericIRQHandler(3);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CTIMER4)
|
||
|
|
void CTIMER4_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
CTIMER_GenericIRQHandler(4);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|