161 lines
7.8 KiB
C
161 lines
7.8 KiB
C
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/*
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* @brief Basic CMSIS include file
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CMSIS_H_
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#define __CMSIS_H_
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#include "lpc_types.h"
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// >>> system config
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#define CHIP_LPC8XX
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#define CHIP_LPC82X
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// <<<
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CMSIS_8XX_ALL CHIP: LPC8xx CMSIS include file
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* @ingroup CHIP_8XX_Drivers
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* @{
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*/
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#if defined(__ARMCC_VERSION)
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// Kill warning "#pragma push with no matching #pragma pop"
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#pragma diag_suppress 2525
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#pragma push
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#pragma anon_unions
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#elif defined(__CWCC__)
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#pragma push
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#pragma cpp_extensions on
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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// #pragma push // FIXME not usable for IAR
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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#if !defined(CORE_M0PLUS)
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#error Please #define CORE_M0PLUS
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#endif
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/** @defgroup CMSIS_8XX CHIP: LPC8xx Cortex CMSIS definitions
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* @ingroup CMSIS_8XX_ALL
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* @{
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*/
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/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
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#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0+ Core Revision */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __VTOR_PRESENT 1 /*!< VTOR is present in this implementation */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @}
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*/
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/** @defgroup CMSIS_8XX_IRQ CHIP: LPC8xx peripheral interrupt numbers
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* @ingroup CMSIS_8XX_ALL
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* @{
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*/
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typedef enum {
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/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
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Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
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/****** LPC8xx Specific Interrupt Numbers ********************************************************/
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SPI0_IRQn = 0, /*!< SPI0 */
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SPI1_IRQn = 1, /*!< SPI1 */
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Reserved0_IRQn = 2, /*!< Reserved Interrupt */
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UART0_IRQn = 3, /*!< USART0 */
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UART1_IRQn = 4, /*!< USART1 */
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UART2_IRQn = 5, /*!< USART2 */
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Reserved1_IRQn = 6, /*!< Reserved Interrupt */
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I2C1_IRQn = 7, /*!< I2C1 */
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I2C0_IRQn = 8, /*!< I2C0 */
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I2C_IRQn = 8, /*!< Alias for I2C0 */
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SCT_IRQn = 9, /*!< SCT */
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MRT_IRQn = 10, /*!< MRT */
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CMP_IRQn = 11, /*!< CMP */
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WDT_IRQn = 12, /*!< WDT */
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BOD_IRQn = 13, /*!< BOD */
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FLASH_IRQn = 14, /*!< Flash interrupt */
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WKT_IRQn = 15, /*!< WKT Interrupt */
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ADC_SEQA_IRQn = 16, /*!< ADC sequence A completion */
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ADC_SEQB_IRQn = 17, /*!< ADC sequence B completion */
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ADC_THCMP_IRQn = 18, /*!< ADC threshold compare */
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ADC_OVR_IRQn = 19, /*!< ADC overrun */
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DMA_IRQn = 20, /*!< Reserved Interrupt */
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I2C2_IRQn = 21, /*!< Reserved Interrupt */
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I2C3_IRQn = 22, /*!< Reserved Interrupt */
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Reserved2_IRQn = 23, /*!< Reserved Interrupt */
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PININT0_IRQn = 24, /*!< External Interrupt 0 */
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PIN_INT0_IRQn = 24, /*!< External Interrupt 0 (alias) */
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PININT1_IRQn = 25, /*!< External Interrupt 1 */
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PIN_INT1_IRQn = 25, /*!< External Interrupt 1 (alias) */
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PININT2_IRQn = 26, /*!< External Interrupt 2 */
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PIN_INT2_IRQn = 26, /*!< External Interrupt 2 (alias) */
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PININT3_IRQn = 27, /*!< External Interrupt 3 */
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PIN_INT3_IRQn = 27, /*!< External Interrupt 3 (alias) */
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PININT4_IRQn = 28, /*!< External Interrupt 4 */
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PIN_INT4_IRQn = 28, /*!< External Interrupt 4 (alias) */
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PININT5_IRQn = 29, /*!< External Interrupt 5 */
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PIN_INT5_IRQn = 29, /*!< External Interrupt 5 (alias) */
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PININT6_IRQn = 30, /*!< External Interrupt 6 */
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PIN_INT6_IRQn = 30, /*!< External Interrupt 6 (alias) */
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PININT7_IRQn = 31, /*!< External Interrupt 7 */
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PIN_INT7_IRQn = 31, /*!< External Interrupt 7 (alias) */
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} IRQn_Type;
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/**
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* @}
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*/
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#include "core_cm0plus.h" /*!< Cortex-M0+ processor and core peripherals */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CMSIS_H_ */
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