397 lines
14 KiB
C
397 lines
14 KiB
C
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/*
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* Copyright 2019-2021 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_MECC_H_
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#define _FSL_MECC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup mecc
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* @{
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*/
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/******************************************************************************
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* Definitions.
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*****************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief Driver version 2.0.2. */
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#define FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U))
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/*@}*/
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/*! @brief Error codes for the MECC driver. */
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enum
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{
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kStatus_MECC_BankMiss = MAKE_STATUS(kStatusGroup_MECC, 0), /*!< Ocram bank miss */
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};
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/*!
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* @brief MECC interrupt configuration structure, default settings all disabled.
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*
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* This structure contains the settings for all of the MECC interrupt configurations.
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*/
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enum
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{
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kMECC_SingleError0InterruptEnable =
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MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt enable.*/
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kMECC_SingleError1InterruptEnable =
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MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt enable*/
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kMECC_SingleError2InterruptEnable =
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MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt enable*/
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kMECC_SingleError3InterruptEnable =
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MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt enable*/
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kMECC_MultiError0InterruptEnable =
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MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt enable*/
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kMECC_MultiError1InterruptEnable =
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MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt enable*/
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kMECC_MultiError2InterruptEnable =
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MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt enable*/
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kMECC_MultiError3InterruptEnable =
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MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt enable*/
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kMECC_StrobeError0InterruptEnable =
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MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt enable*/
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kMECC_StrobeError1InterruptEnable =
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MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt enable*/
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kMECC_StrobeError2InterruptEnable =
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MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt enable*/
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kMECC_StrobeError3InterruptEnable =
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MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt enable*/
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kMECC_AccessError0InterruptEnable =
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MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt enable*/
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kMECC_AccessError1InterruptEnable =
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MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt enable*/
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kMECC_AccessError2InterruptEnable =
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MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt enable*/
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kMECC_AccessError3InterruptEnable =
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MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt enable*/
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kMECC_AllInterruptsEnable = 0xFFFF, /*!< all interrupts enable */
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};
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/*!
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* @brief MECC interrupt status configuration structure, default settings all disabled.
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*
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* This structure contains the settings for all of the MECC interrupt status configurations.
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*/
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enum
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{
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kMECC_SingleError0InterruptStatusEnable =
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MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt status enable.*/
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kMECC_SingleError1InterruptStatusEnable =
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MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt status enable*/
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kMECC_SingleError2InterruptStatusEnable =
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MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt status enable*/
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kMECC_SingleError3InterruptStatusEnable =
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MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt status enable*/
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kMECC_MultiError0InterruptStatusEnable =
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MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt status enable*/
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kMECC_MultiError1InterruptStatusEnable =
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MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt status enable*/
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kMECC_MultiError2InterruptStatusEnable =
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MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt status enable*/
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kMECC_MultiError3InterruptStatusEnable =
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MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt status enable*/
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kMECC_StrobeError0InterruptStatusEnable =
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MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt status enable*/
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kMECC_StrobeError1InterruptStatusEnable =
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MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt status enable*/
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kMECC_StrobeError2InterruptStatusEnable =
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MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt status enable*/
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kMECC_StrobeError3InterruptStatusEnable =
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MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt status enable*/
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kMECC_AccessError0InterruptStatusEnable =
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MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt status enable*/
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kMECC_AccessError1InterruptStatusEnable =
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MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt status enable*/
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kMECC_AccessError2InterruptStatusEnable =
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MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt status enable*/
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kMECC_AccessError3InterruptStatusEnable =
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MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt status enable*/
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kMECC_AllInterruptsStatusEnable = 0xFFFF, /*!< all interrupts enable */
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};
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/*!
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* @brief MECC status flags.
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*
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* This provides constants for the MECC status flags for use in the MECC functions.
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*/
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enum
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{
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kMECC_SingleError0InterruptFlag =
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MECC_ERR_STATUS_SINGLE_ERR0_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt flag*/
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kMECC_SingleError1InterruptFlag =
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MECC_ERR_STATUS_SINGLE_ERR1_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt flag*/
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kMECC_SingleError2InterruptFlag =
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MECC_ERR_STATUS_SINGLE_ERR2_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt flag*/
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kMECC_SingleError3InterruptFlag =
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MECC_ERR_STATUS_SINGLE_ERR3_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt flag*/
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kMECC_MultiError0InterruptFlag =
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MECC_ERR_STATUS_MULTI_ERR0_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt flag*/
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kMECC_MultiError1InterruptFlag =
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MECC_ERR_STATUS_MULTI_ERR1_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt flag*/
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kMECC_MultiError2InterruptFlag =
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MECC_ERR_STATUS_MULTI_ERR2_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt flag*/
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kMECC_MultiError3InterruptFlag =
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MECC_ERR_STATUS_MULTI_ERR3_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt flag*/
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kMECC_StrobeError0InterruptFlag =
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MECC_ERR_STATUS_STRB_ERR0_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt flag*/
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kMECC_StrobeError1InterruptFlag =
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MECC_ERR_STATUS_STRB_ERR1_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt flag*/
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kMECC_StrobeError2InterruptFlag =
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MECC_ERR_STATUS_STRB_ERR2_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt flag*/
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kMECC_StrobeError3InterruptFlag =
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MECC_ERR_STATUS_STRB_ERR3_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt flag*/
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kMECC_AccessError0InterruptFlag = MECC_ERR_STATUS_ADDR_ERR0_MASK, /*!< Ocram Access Error On Bank0 interrupt flag*/
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kMECC_AccessError1InterruptFlag = MECC_ERR_STATUS_ADDR_ERR1_MASK, /*!< Ocram Access Error On Bank1 interrupt flag*/
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kMECC_AccessError2InterruptFlag = MECC_ERR_STATUS_ADDR_ERR2_MASK, /*!< Ocram Access Error On Bank2 interrupt flag*/
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kMECC_AccessError3InterruptFlag = MECC_ERR_STATUS_ADDR_ERR3_MASK, /*!< Ocram Access Error On Bank3 interrupt flag*/
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kMECC_AllInterruptsFlag = 0xFFFF, /*!< all interrupts interrupt flag */
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};
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/*! @brief MECC ocram bank number */
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enum
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{
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kMECC_OcramBank0 = 0U, /*!< ocram bank number 0: ocram_base_address+0x20*i */
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kMECC_OcramBank1 = 1U, /*!< ocram bank number 1: ocram_base_address+0x20*i+0x8 */
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kMECC_OcramBank2 = 2U, /*!< ocram bank number 2: ocram_base_address+0x20*i+0x10 */
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kMECC_OcramBank3 = 3U, /*!< ocram bank number 3: ocram_base_address+0x20*i+0x18 */
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};
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/*! @brief MECC instance */
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enum
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{
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kMECC_Instance0 = 0U, /*!< Peripheral MECC1 base */
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kMECC_Instance1 = 1U, /*!< Peripheral MECC2 base */
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};
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/*! @brief MECC user configuration.*/
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typedef struct _mecc_config
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{
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bool enableMecc; /*!< Enable the MECC function. */
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uint32_t Ocram1StartAddress; /*!< Ocram 1 start address. */
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uint32_t Ocram1EndAddress; /*!< Ocram 1 end address. */
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uint32_t Ocram2StartAddress; /*!< Ocram 2 start address. */
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uint32_t Ocram2EndAddress; /*!< Ocram 2 end address. */
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} mecc_config_t;
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/*! @brief MECC ocram single error information, including single error address, ECC code, error data and error bit
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* position */
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typedef struct _mecc_single_error_info
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{
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uint32_t singleErrorAddress; /*!< Single error address on Ocram bank n */
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uint32_t singleErrorDataLow; /*!< Single error low 32 bits uncorrected read data on Ocram bank n */
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uint32_t singleErrorDataHigh; /*!< Single error high 32 bits uncorrected read data on Ocram bank n */
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uint32_t singleErrorPosLow; /*!< Single error bit postion of low 32 bits read data on Ocram bank n */
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uint32_t singleErrorPosHigh; /*!< Single error bit postion of high 32 bits read data on Ocram bank n */
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uint8_t singleErrorEccCode; /*!< Single error ECC code on Ocram bank n */
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} mecc_single_error_info_t;
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/*! @brief MECC ocram multiple error information, including multiple error address, ECC code, error data */
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typedef struct _mecc_multi_error_info
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{
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uint32_t multiErrorAddress; /*!< Multiple error address on Ocram bank n */
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uint32_t multiErrorDataLow; /*!< Multiple error low 32 bits read data on Ocram bank n */
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uint32_t multiErrorDataHigh; /*!< Multiple error high 32 bits read data on Ocram bank n */
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uint8_t multiErrorEccCode; /*!< Multiple error ECC code on Ocram bank n */
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} mecc_multi_error_info_t;
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/*******************************************************************************
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* APIs
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief MECC module initialization function.
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*
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* @param base MECC base address.
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* @param config pointer to the MECC configuration structure.
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*/
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void MECC_Init(MECC_Type *base, mecc_config_t *config);
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/*!
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* @brief Deinitializes the MECC.
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*
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* @param base MECC base address.
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*/
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void MECC_Deinit(MECC_Type *base);
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/*!
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* @brief Sets the MECC configuration structure to default values.
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*
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* @param config pointer to the MECC configuration structure.
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*/
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void MECC_GetDefaultConfig(mecc_config_t *config);
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/* @} */
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/*!
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* @name Status
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* @{
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*/
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/*!
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* @brief Gets MECC status flags.
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*
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* @param base MECC peripheral base address.
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* @return MECC status flags.
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*/
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static inline uint32_t MECC_GetStatusFlags(MECC_Type *base)
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{
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return base->ERR_STATUS & (uint32_t)kMECC_AllInterruptsFlag;
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}
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/*!
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* @brief MECC module clear interrupt status.
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*
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* @param base MECC base address.
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* @param mask status to clear.
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*/
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static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask)
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{
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base->ERR_STATUS = mask;
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}
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/*!
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* @brief MECC module enable interrupt status.
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*
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* @param base MECC base address.
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* @param mask status to enable.
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*/
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static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask)
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{
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base->ERR_STAT_EN |= mask;
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}
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/*!
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* @brief MECC module disable interrupt status.
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*
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* @param base MECC base address.
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* @param mask status to disable.
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*/
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static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask)
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{
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base->ERR_STAT_EN &= ~mask;
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}
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/* @} */
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/*!
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* @name Interrupts
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* @{
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*/
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/*!
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* @brief MECC module enable interrupt.
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*
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* @param base MECC base address.
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* @param mask The interrupts to enable.
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*/
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static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask)
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{
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base->ERR_SIG_EN |= mask;
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}
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/*!
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* @brief MECC module disable interrupt.
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*
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* @param base MECC base address.
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* @param mask The interrupts to disable.
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*/
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static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask)
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{
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base->ERR_SIG_EN &= ~mask;
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}
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/* @} */
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/*!
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* @name functional
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* @{
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*/
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/*!
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* @brief MECC module error injection.
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*
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* @param base MECC base address.
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* @param lowerrordata low 32 bits data.
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* @param higherrordata high 32 bits data.
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* @param eccdata ecc code.
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||
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* @param banknumber ocram bank number.
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* @retval kStatus_Success.
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||
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|
*
|
||
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* Bank0: ocram_base_address+0x20*i
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||
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* Bank1: ocram_base_address+0x20*i+0x8
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||
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* Bank2: ocram_base_address+0x20*i+0x10
|
||
|
|
* Bank3: ocram_base_address+0x20*i+0x18
|
||
|
|
* i = 0,1,2,3,4.....
|
||
|
|
*/
|
||
|
|
status_t MECC_ErrorInjection(
|
||
|
|
MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber);
|
||
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|
|
||
|
|
/*!
|
||
|
|
* @brief MECC module get single error information.
|
||
|
|
*
|
||
|
|
* @param base MECC base address.
|
||
|
|
* @param info single error information.
|
||
|
|
* @param banknumber ocram bank number.
|
||
|
|
* @retval kStatus_Success.
|
||
|
|
* @retval kStatus_MECC_BankMiss.
|
||
|
|
*
|
||
|
|
* Bank0: ocram_base_address+0x20*i
|
||
|
|
* Bank1: ocram_base_address+0x20*i+0x8
|
||
|
|
* Bank2: ocram_base_address+0x20*i+0x10
|
||
|
|
* Bank3: ocram_base_address+0x20*i+0x18
|
||
|
|
* i = 0,1,2,3,4.....
|
||
|
|
*/
|
||
|
|
status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief MECC module get multiple error information.
|
||
|
|
*
|
||
|
|
* @param base MECC base address.
|
||
|
|
* @param info multiple error information.
|
||
|
|
* @param banknumber ocram bank number.
|
||
|
|
* @retval kStatus_Success.
|
||
|
|
* @retval kStatus_MECC_BankMiss.
|
||
|
|
*
|
||
|
|
* Bank0: ocram_base_address+0x20*i
|
||
|
|
* Bank1: ocram_base_address+0x20*i+0x8
|
||
|
|
* Bank2: ocram_base_address+0x20*i+0x10
|
||
|
|
* Bank3: ocram_base_address+0x20*i+0x18
|
||
|
|
* i = 0,1,2,3,4.....
|
||
|
|
*/
|
||
|
|
status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber);
|
||
|
|
|
||
|
|
/*! @}*/
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*! @}*/
|
||
|
|
|
||
|
|
#endif
|