365 lines
13 KiB
C
365 lines
13 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi_edma.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexspi_edma"
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#endif
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/*<! Structure definition for flexspi_edma_private_handle_t. The structure is private. */
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typedef struct _flexspi_edma_private_handle
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{
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FLEXSPI_Type *base;
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flexspi_edma_handle_t *handle;
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} flexspi_edma_private_handle_t;
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/* FLEXSPI EDMA transfer handle, _flexspi_edma_tansfer_states. */
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enum
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{
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kFLEXSPI_Idle, /* FLEXSPI Bus idle. */
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kFLEXSPI_Busy /* FLEXSPI Bus busy. */
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};
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to flexspi bases for each instance. */
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static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
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/*<! Private handle only used for internally. */
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static flexspi_edma_private_handle_t s_edmaPrivateHandle[ARRAY_SIZE(s_flexspiBases)];
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief FLEXSPI EDMA transfer finished callback function.
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*
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* This function is called when FLEXSPI EDMA transfer finished. It disables the FLEXSPI
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* TX/RX EDMA request and sends status to FLEXSPI callback.
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*
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* @param handle The EDMA handle.
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* @param param Callback function parameter.
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*/
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static void FLEXSPI_TransferEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint8_t FLEXSPI_CalculatePower(uint8_t value)
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{
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uint8_t power = 0;
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while (value >> 1 != 0U)
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{
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power++;
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value = value >> 1;
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}
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return power;
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}
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static void FLEXSPI_TransferEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
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{
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flexspi_edma_private_handle_t *flexspiPrivateHandle = (flexspi_edma_private_handle_t *)param;
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/* Avoid warning for unused parameters. */
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handle = handle;
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tcds = tcds;
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if (transferDone)
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{
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(flexspiPrivateHandle->base))
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{
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}
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/* Disable transfer. */
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FLEXSPI_TransferAbortEDMA(flexspiPrivateHandle->base, flexspiPrivateHandle->handle);
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if (flexspiPrivateHandle->handle->completionCallback != NULL)
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{
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flexspiPrivateHandle->handle->completionCallback(flexspiPrivateHandle->base, flexspiPrivateHandle->handle,
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kStatus_Success, flexspiPrivateHandle->handle->userData);
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}
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}
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}
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/*!
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* brief Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback.
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*
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* param base FLEXSPI peripheral base address
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* param handle Pointer to flexspi_edma_handle_t structure
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* param callback FLEXSPI callback, NULL means no callback.
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* param userData User callback function data.
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* param txDmaHandle User requested DMA handle for TX DMA transfer.
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* param rxDmaHandle User requested DMA handle for RX DMA transfer.
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*/
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void FLEXSPI_TransferCreateHandleEDMA(FLEXSPI_Type *base,
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flexspi_edma_handle_t *handle,
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flexspi_edma_callback_t callback,
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void *userData,
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edma_handle_t *txDmaHandle,
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edma_handle_t *rxDmaHandle)
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{
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assert(handle);
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uint32_t instance = FLEXSPI_GetInstance(base);
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s_edmaPrivateHandle[instance].base = base;
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s_edmaPrivateHandle[instance].handle = handle;
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(void)memset(handle, 0, sizeof(*handle));
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handle->state = kFLEXSPI_Idle;
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handle->txDmaHandle = txDmaHandle;
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handle->rxDmaHandle = rxDmaHandle;
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handle->nsize = kFLEXPSI_EDMAnSize1Bytes;
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handle->completionCallback = callback;
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handle->userData = userData;
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}
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/*!
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* brief Update FLEXSPI EDMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE).
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*
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* param base FLEXSPI peripheral base address
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* param handle Pointer to flexspi_edma_handle_t structure
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* param nsize FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is
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* kFLEXPSI_EDMAnSize1Bytes(one byte).
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* see flexspi_edma_transfer_nsize_t .
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*/
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void FLEXSPI_TransferUpdateSizeEDMA(FLEXSPI_Type *base,
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flexspi_edma_handle_t *handle,
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flexspi_edma_transfer_nsize_t nsize)
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{
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handle->nsize = nsize;
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}
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/*!
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* brief Transfers FLEXSPI data using an eDMA non-blocking method.
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*
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* This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking.
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* param base FLEXSPI peripheral base address.
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* param handle Pointer to flexspi_edma_handle_t structure
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* param xfer FLEXSPI transfer structure.
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* retval kStatus_FLEXSPI_Busy FLEXSPI is busy transfer.
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* retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark should be power of
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2 to do successfully EDMA transfer.
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* retval kStatus_Success FLEXSPI successfully start edma transfer.
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*/
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status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_transfer_t *xfer)
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{
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uint32_t configValue = 0;
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status_t result = kStatus_Success;
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edma_transfer_config_t xferConfig;
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uint32_t instance = FLEXSPI_GetInstance(base);
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uint8_t power = 0;
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assert(handle);
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assert(xfer);
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/* Check if the FLEXSPI bus is idle - if not return busy status. */
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if (handle->state != (uint32_t)kFLEXSPI_Idle)
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{
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result = kStatus_FLEXSPI_Busy;
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}
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else
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{
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handle->transferSize = xfer->dataSize;
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handle->state = kFLEXSPI_Busy;
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/* Clear sequence pointer before sending data to external devices. */
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base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
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/* Clear former pending status before start this transfer. */
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base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
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FLEXSPI_INTR_IPCMDGE_MASK;
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/* Configure base address. */
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base->IPCR0 = xfer->deviceAddress;
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/* Reset fifos. */
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base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
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base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
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/* Configure data size. */
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if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write))
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{
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configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize);
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}
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/* Configure sequence ID. */
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configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U);
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base->IPCR1 = configValue;
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}
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if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config))
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{
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handle->count = (uint8_t)((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U;
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if (xfer->dataSize < 8U * (uint32_t)handle->count)
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{
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handle->nbytes = (uint8_t)xfer->dataSize;
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}
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else
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{
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/* Check the handle->count is power of 2 */
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if (((handle->count) & (handle->count - 1U)) != 0U)
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{
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return kStatus_InvalidArgument;
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}
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/* Store the initially configured eDMA minor byte transfer count into the FLEXSPI handle */
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handle->nbytes = (8U * handle->count);
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}
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power = FLEXSPI_CalculatePower(8U * handle->count);
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/* Prepare transfer. */
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EDMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t)handle->nsize,
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(void *)(uint32_t *)FLEXSPI_GetTxFifoAddress(base), (uint32_t)handle->nsize,
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(uint32_t)handle->nbytes, xfer->dataSize, kEDMA_MemoryToMemory);
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/* Submit transfer. */
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(void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
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handle->txDmaHandle->base->TCD[handle->txDmaHandle->channel].ATTR |= DMA_ATTR_DMOD(power);
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EDMA_SetCallback(handle->txDmaHandle, FLEXSPI_TransferEDMACallback,
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&s_edmaPrivateHandle[FLEXSPI_GetInstance(base)]);
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EDMA_StartTransfer(handle->txDmaHandle);
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/* Enable FLEXSPI TX EDMA. */
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FLEXSPI_EnableTxDMA(base, true);
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/* Start Transfer. */
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base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
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}
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else if (xfer->cmdType == kFLEXSPI_Read)
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{
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handle->count = (uint8_t)((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U;
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if (xfer->dataSize < 8U * (uint32_t)handle->count)
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{
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handle->nbytes = (uint8_t)xfer->dataSize;
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}
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else
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{
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/* Check the handle->count is power of 2 */
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if (((handle->count) & (handle->count - 1U)) != 0U)
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{
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return kStatus_InvalidArgument;
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}
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/* Store the initially configured eDMA minor byte transfer count into the FLEXSPI handle */
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handle->nbytes = (8U * handle->count);
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}
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power = FLEXSPI_CalculatePower(8U * handle->count);
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/* Prepare transfer. */
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EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)FLEXSPI_GetRxFifoAddress(base), (uint32_t)handle->nsize,
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xfer->data, (uint32_t)handle->nsize, (uint32_t)handle->nbytes, xfer->dataSize,
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kEDMA_MemoryToMemory);
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/* Submit transfer. */
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(void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
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handle->rxDmaHandle->base->TCD[handle->rxDmaHandle->channel].ATTR |= DMA_ATTR_SMOD(power);
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EDMA_SetCallback(handle->rxDmaHandle, FLEXSPI_TransferEDMACallback, &s_edmaPrivateHandle[instance]);
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EDMA_StartTransfer(handle->rxDmaHandle);
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/* Enable FLEXSPI RX EDMA. */
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FLEXSPI_EnableRxDMA(base, true);
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/* Start Transfer. */
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base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
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}
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else
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{
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/* Start Transfer. */
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base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(base))
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{
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}
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result = FLEXSPI_CheckAndClearError(base, base->INTR);
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handle->state = kFLEXSPI_Idle;
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if (handle->completionCallback != NULL)
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{
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handle->completionCallback(base, handle, result, handle->userData);
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}
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}
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return result;
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}
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/*!
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* brief Aborts the transfer data using eDMA.
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*
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* This function aborts the transfer data using eDMA.
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*
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* param base FLEXSPI peripheral base address.
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* param handle Pointer to flexspi_edma_handle_t structure
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*/
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void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle)
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{
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assert(handle);
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if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U)
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{
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FLEXSPI_EnableTxDMA(base, false);
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EDMA_AbortTransfer(handle->txDmaHandle);
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}
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if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U)
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{
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FLEXSPI_EnableRxDMA(base, false);
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EDMA_AbortTransfer(handle->rxDmaHandle);
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}
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handle->state = kFLEXSPI_Idle;
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}
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status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count)
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{
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assert(handle);
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assert(count);
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status_t result = kStatus_Success;
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if (handle->state != (uint32_t)kFLEXSPI_Busy)
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{
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result = kStatus_NoTransferInProgress;
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}
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else
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{
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if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U)
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{
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*count = (handle->transferSize -
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(uint32_t)handle->nbytes *
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EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel));
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}
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else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U)
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{
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*count = (handle->transferSize -
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(uint32_t)handle->nbytes *
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EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel));
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}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
; /* Intentional empty for MISRA C-2012 rule 15.7. */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|