93 lines
3.0 KiB
C
93 lines
3.0 KiB
C
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/*
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* Copyright 2019-2021 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexram_allocate.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.soc_flexram_allocate"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*!
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* brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
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* This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
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* is needed.
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* param config allocate configuration.
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* retval kStatus_InvalidArgument the argument is invalid
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* kStatus_Success allocate success
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*/
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status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
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{
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assert(config != NULL);
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uint8_t dtcmBankNum = config->dtcmBankNum;
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uint8_t itcmBankNum = config->itcmBankNum;
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uint8_t ocramBankNum = config->ocramBankNum;
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uint8_t i = 0U;
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uint32_t bankCfg = 0U;
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status_t status = kStatus_Success;
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uint32_t tempGPR17 = 0U;
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uint32_t tempGPR18 = 0U;
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/* check the arguments */
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if ((uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum))
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{
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status = kStatus_InvalidArgument;
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}
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else
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{
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/* flexram bank config value */
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for (i = 0U; i < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++)
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{
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if (i < ocramBankNum)
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{
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bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2U);
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continue;
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}
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if (i < (dtcmBankNum + ocramBankNum))
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{
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bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2U);
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continue;
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}
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if (i < (dtcmBankNum + ocramBankNum + itcmBankNum))
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{
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bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2U);
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continue;
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}
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}
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tempGPR17 = IOMUXC_GPR->GPR17;
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tempGPR18 = IOMUXC_GPR->GPR18;
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IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU);
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IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) & 0xFFFFU);
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/* select ram allocate source from FLEXRAM_BANK_CFG */
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FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg);
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}
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return status;
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}
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