201 lines
6.4 KiB
C
201 lines
6.4 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_dac12.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.dac12"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for DAC12 module.
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*
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* @param base DAC12 peripheral base address
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*/
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static uint32_t DAC12_GetInstance(DAC_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to DAC bases for each instance. */
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static DAC_Type *const s_dac12Bases[] = DAC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to DAC clocks for each instance. */
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static const clock_ip_name_t s_dac12Clocks[] = DAC_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Codes
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******************************************************************************/
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static uint32_t DAC12_GetInstance(DAC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_dac12Bases); instance++)
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{
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if (s_dac12Bases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_dac12Bases));
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return instance;
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}
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/*!
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* brief Get hardware information about this module.
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*
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* param base DAC12 peripheral base address.
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* param info Pointer to info structure, see to #dac12_hardware_info_t.
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*/
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void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info)
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{
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assert(NULL != info);
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info->fifoSizeInfo =
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(dac12_fifo_size_info_t)(uint32_t)((DAC_PARAM_FIFOSZ_MASK & base->PARAM) >> DAC_PARAM_FIFOSZ_SHIFT);
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}
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/*!
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* brief Initialize the DAC12 module.
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*
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* param base DAC12 peripheral base address.
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* param config Pointer to configuration structure, see to #dac12_config_t.
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*/
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void DAC12_Init(DAC_Type *base, const dac12_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(s_dac12Clocks[DAC12_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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tmp32 = DAC_CR_WML(config->fifoWatermarkLevel); /* FIFO watermark level. */
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switch (config->fifoWorkMode) /* FIFO work mode. */
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{
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case kDAC12_FIFOWorkAsNormalMode:
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tmp32 |= DAC_CR_FIFOEN_MASK;
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break;
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case kDAC12_FIFOWorkAsSwingMode:
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tmp32 |= DAC_CR_FIFOEN_MASK | DAC_CR_SWMD_MASK;
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break;
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default: /* kDAC12_FIFODisabled. */
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break;
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}
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tmp32 |= DAC_CR_DACRFS(config->referenceVoltageSource) /* Reference voltage source. */
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| DAC_CR_TRGSEL(config->fifoTriggerMode); /* Trigger mode. */
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base->CR = tmp32;
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/* DACx_CR2. */
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tmp32 = 0U;
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/* Reference voltage current. */
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switch (config->referenceCurrentSource)
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{
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case kDAC12_ReferenceCurrentSourceAlt0:
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tmp32 |= DAC_CR2_IREF_MASK;
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break;
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case kDAC12_ReferenceCurrentSourceAlt1:
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tmp32 |= DAC_CR2_IREF1_MASK;
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break;
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case kDAC12_ReferenceCurrentSourceAlt2:
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tmp32 |= DAC_CR2_IREF2_MASK;
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break;
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default: /* kDAC12_ReferenceCurrentSourceDisabled */
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break;
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}
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/* Speed mode. */
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switch (config->speedMode)
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{
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case kDAC12_SpeedMiddleMode:
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tmp32 |= DAC_CR2_BFMS_MASK;
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break;
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case kDAC12_SpeedHighMode:
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tmp32 |= DAC_CR2_BFHS_MASK;
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break;
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default: /* kDAC12_SpeedLowMode */
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break;
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}
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/* DAC buffered mode needs OPAMP enabled. DAC unbuffered mode needs OPAMP disabled. */
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if (config->enableAnalogBuffer)
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{
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tmp32 |= DAC_CR2_BFEN_MASK; /* OPAMP is used as buffer. */
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}
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else
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{
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tmp32 |= DAC_CR2_OEN_MASK; /* Output buffer is bypassed. */
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}
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base->CR2 = tmp32;
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#if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER)
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base->ITRM = DAC_ITRM_TRIM(config->currentReferenceInternalTrimValue);
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#endif /* FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER */
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}
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/*!
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* brief De-initialize the DAC12 module.
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*
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* param base DAC12 peripheral base address.
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*/
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void DAC12_Deinit(DAC_Type *base)
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{
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DAC12_Enable(base, false);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_DisableClock(s_dac12Clocks[DAC12_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Initializes the DAC12 user configuration structure.
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*
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* This function initializes the user configuration structure to a default value. The default values are:
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* code
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* config->fifoWatermarkLevel = 0U;
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* config->fifoWorkMode = kDAC12_FIFODisabled;
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* config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1;
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* config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode;
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* config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0;
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* config->speedMode = kDAC12_SpeedLowMode;
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* config->speedMode = false;
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* config->currentReferenceInternalTrimValue = 0x4;
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* endcode
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* param config Pointer to the configuration structure. See "dac12_config_t".
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*/
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void DAC12_GetDefaultConfig(dac12_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->fifoWatermarkLevel = 0U;
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config->fifoWorkMode = kDAC12_FIFODisabled;
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config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1;
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config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode;
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config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0;
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config->speedMode = kDAC12_SpeedLowMode;
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config->enableAnalogBuffer = false;
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#if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER)
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config->currentReferenceInternalTrimValue = 0x4;
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#endif /* FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER */
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}
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