179 lines
9.7 KiB
Markdown
179 lines
9.7 KiB
Markdown
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# CAT1 (PSoC™ 6) Hardware Abstraction Layer (HAL) Release Notes
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The CAT1 Hardware Abstraction Layer (HAL) provides an implementation of the Hardware Abstraction Layer for the PSoC™ 6 family of chips. This API provides convenience methods for initializing and manipulating different hardware peripherals. Depending on the specific chip being used, not all features may be supported.
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This library is only supported on the Cortex-M4. It is not compatible with the Cortex-M0+. Any peripherals used by the Cortex-M0+ must be configured using the PDL and reserved on the Cortex-M4 by calling cyhal_hwmgr_reserve(). This ensures the HAL is aware the resource is in use and does not overuse it.
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### What's Included?
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This release of the CAT1 HAL includes support for the following drivers:
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* ADC
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* Clock
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* Comparator
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* CRC
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* DAC
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* DMA
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* EZ-I2C
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* Flash
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* GPIO
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* Hardware Manager
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* I2C
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* I2S
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* LowPower Timer (LPTimer)
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* OpAmp
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* PDM/PCM
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* Power Management (SysPM)
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* PWM
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* QSPI
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* Quadrature Decoder (QuadDec)
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* RTC
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* SDHC
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* SDIO
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* SPI
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* System
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* TDM
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* Timer
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* True Random Number Generator (TRNG)
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* UART
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* USB Device
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* WDT
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### What Changed?
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#### v2.1.0
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* Pre-production support for CAT1B devices
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* Fixed a few bugs in various drivers
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#### v2.0.1
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This patch release addresses issues in several drivers:
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* RTC:
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1. Do not use RTOS delay even in RTOS-aware mode, to avoid ordering requirements between RTC and RTOS init.
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* PWM:
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1. Fix incorrect period/duty cycle calculation when a `line_n` (inverted) output pin is used as the sole,
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non-inverted PWM output.
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* PWM/Timer/QuadDec
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1. Fix level/edge nature of the source not being honored in `cyhal_*_connect_digital`.
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2. Add `cyhal_*_connect_digital2` API to allow explicitly specifying edge type (rising/falling/both). This supercedes
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`cyhal_connect_digital`, which defaults to rising edge when the source is an "edge" signal.
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#### v2.0.0
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This major version update includes changes that break API compatibility with prior releases. Each major or breaking change is described below:
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* Clock:
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1. Renamed cyhal_resource_inst_t CYHAL_CLOCK_<name> constants with CYHAL_CLOCK_RSC_<name>. Created new CYHAL_CLOCK_<name> constants of type cyhal_clock_t.
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2. Replaced cyhal_clock_init with cyhal_clock_reserve.
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3. Removed div_type & div_num from cyhal_clock_t.
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* DMA:
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1. cyhal_dma_enable must be called after configuring the DMA, but before a trigger will initiate a transfer
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* Flash:
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1. The data buffer passed to functions must be from SRAM, the driver no longer contains a scratch buffer to copy into.
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* GPIO:
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1. cyhal_gpio_enable_output updated to require a new argument to specify whether the signal is level or edge based.
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2. cyhal_gpio_connect_digital no longer takes the signal type parameter.
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3. cyhal_gpio_register_callback now takes a structure containing details about the callback.
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4. Removed deprecated functions cyhal_gpio_register_irq & cyhal_gpio_irq_enable
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* I2C:
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1. Removed deprecated functions cyhal_i2c_register_irq & cyhal_i2c_irq_enable
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* I2S/TDM:
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1. The mclk GPIO selection is moved into the RX/TX specific pins struct. This allows RX and TX to use separate mclk pins on devices that support this;
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see the device datasheet for details. For devices which only support a single MCLK pin shared between RX and TX, there is no change in functionality; when
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calling `cyhal_i2s_init` or `cyhal_tdm_init` the same `cyhal_gpio_t` value should be provided for both RX and TX.
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* PWM:
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1. cyhal_pwm_connect_digital no longer takes the signal type parameter.
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2. cyhal_pwm_init will always produce a non-inverted waveform on the specified pin, even if that pin natively produces an inverted
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output (for example, the `line_compl` pins on PSoC™ devices). This improves consistency with the behavior of cyhal_pwm_init_adv.
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* QSPI:
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1. cyhal_qspi_init() function got one additional parameter - shared clock (clk), which will allow users to use multiple HAL drivers which depends on same clock source.
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2. cyhal_qspi_init() now takes io[x] and ssel pins as pointer to cyhal_qspi_slave_pin_config_t structure, that contain mentioned pins.
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3. cyhal_qspi_slave_select_config function was replaced by cyhal_qspi_slave_configure, which provides possibility to add memory slaves with own data lines (instead of shared data lines and own slave select like it was when cyhal_qspi_slave_select_config has been used). cyhal_qspi_slave_config, as cyhal_qspi_init, takes cyhal_qspi_slave_pin_config_t as parameter.
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4. cyhal_qspi_command_t structure was updated: address.value field removed, data_rate field was added into all command subsections.
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5. Added address parameter to all transfer functions (cyhal_qspi_read, cyhal_qspi_read_async, cyhal_qspi_write, cyhal_qspi_write_async anb cyhal_qspi_transfer).
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6. cyhal_qspi_datarate_t enum was added. Corresponding configuration fields are added into each sub-structure of cyhal_qspi_command_t.
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* SDHC:
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1. cyhal_sdhc_init() and cyhal_sdhc_init_hw() functions got one additional parameter - shared clock (block_clk), which will allow users to use multiple HAL drivers which depends on same clock source.
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* SDIO:
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1. Updated the names of enum cyhal_tranfer_t and its types CYHAL_READ and CYHAL_WRITE to cyhal_sdio_transfer_type_t, CYHAL_SDIO_XFER_TYPE_READ, and CYHAL_SDIO_XFER_TYPE_WRITE, respectively.
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2. Removed deprecated functions cyhal_sdio_register_irq & cyhal_sdio_irq_enable
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* Timer:
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1. cyhal_timer_connect_digital no longer takes the signal type parameter.
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* UART:
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1. cyhal_uart_set_flow_control function was replaced by cyhal_uart_enable_flow_control, which only controls the enablement status of flow control. CTS / RTS pins are now provided via cyhal_uart_init() function.
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* I2C:
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1. The following deprecated functions have been removed: cyhal_i2c_slave_config_write_buff, cyhal_i2c_slave_config_read_buff.
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* Other:
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1. Removed cyhal_deprecated.h, and all associated code.
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NOTE: This version requires core-lib 1.3.0 or later
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#### v1.6.0
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* Added new TDM driver
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* Added support for 1.8v devices to SDHC/SDIO drivers
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* Extended System driver to support registering for other interrupts
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* Fixed issues with level trigger signals to the DMA driver
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* Fixed a few bugs in various drivers
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#### v1.5.0
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* Added new Quadrature Decoder (QuadDec) driver
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* Added digital hardware connection APIs to drivers
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* Fixed a few bugs in various drivers
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* Updated SDHC and MXSDHC-based SDIO communication functions to use semaphores in RTOS aware environments for improved performance
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* Added optional implementations for SDHC control pin APIs and RTOS aware delay API provided as weak functions in the PDL (Disabled by: DEFINES+=CYHAL_DISABLE_WEAK_FUNC_IMPL)
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#### v1.4.0
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* Renamed library from psoc6hal to mtb-hal-cat1
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* Added support for new PSoC™ 6 S4 devices
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* Extended clock support for QSPI and SDHC drivers
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* Fixed a few bugs in various drivers
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* Minor documentation updates
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#### v1.3.0
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* Added new Analog Comparator driver
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* Added new OpAmp driver
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* Extended ADC driver
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* Extended DAC driver
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* Extended SPI/QSPI drivers to support multiple slave select signals
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* Fixed SDHC based SDIO cyhal_sdio_is_busy() function to return status immediately instead of waiting until the transfer completes
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* Fixed a few bugs in various drivers
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* Minor update for documentation & branding
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#### v1.2.1
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* Added new option for SysPM driver to support tickless sleep in addition to deepsleep
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* Fixed an issue with deep-sleep wake-up in the SDIO and SDHC drivers that could cause intermittent communication failures
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* Minor bug fixes and documentation improvements
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#### v1.2.0
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* Added new Clock driver
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* Added new SysPM Power Management driver
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* Added new I2S driver
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* Added new PDM/PCM driver
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* Reduced flash memory usage for a number of drivers
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* Improved documentation for a number of drivers
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* Fixed a few bugs in various drivers
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NOTE: The new SysPM driver needs to be initialized by calling cyhal_syspm_init(). This is done automatically by Board Support Packages version 1.2.0 and later.
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#### v1.1.1
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* Improved documentation for a number of drivers
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* Fixed duplicate symbol definition with PDL 1.4.1 release
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* Minor bug fixes
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#### v1.1.0
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* Added new DMA driver
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* Added new EZ-I2C driver
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* Extended System driver to allow getting information about reset
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* Extended System driver to provide delay functions
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* Updated PWM driver to provide additional configuration options
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* Updated Timer driver to allow reading the current count
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* Updated RTC driver to support Day Light Savings time
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* Updated LP Timer driver to improve performance
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* Minor updates up avoid potential warnings on some toolchains
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* Multiple bug fixes across drivers
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#### v1.0.0
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* Initial release (ADC, CRC, DAC, Flash, GPIO, Hardware Manager, I2C, LP Timer, PWM, QSPI, RTC, SDHC, SDIO, SPI, System, Timer, TRNG, UART, USB Device, WDT)
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### Supported Software and Tools
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This version of the CAT1 Hardware Abstraction Layer was validated for compatibility with the following Software and Tools:
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| Software and Tools | Version |
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| :--- | :----: |
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| ModusToolbox™ Software Environment | 2.4.0 |
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| GCC Compiler | 10.3.1 |
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| IAR Compiler | 8.4 |
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| ARM Compiler | 6.11 |
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Minimum required ModusToolbox™ Software Environment: v2.0
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### More information
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Use the following links for more information, as needed:
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* [API Reference Guide](https://infineon.github.io/mtb-hal-cat1/html/modules.html)
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* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
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* [Infineon GitHub](https://github.com/infineon)
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* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
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---
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© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021.
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