191 lines
7.5 KiB
C
191 lines
7.5 KiB
C
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/******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_sram.h
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**
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** A detailed description is available at
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** @link SramGroup Internal SRAM description @endlink
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**
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** - 2018-10-17 CDT First version for Device Driver Library of SRAM.
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**
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******************************************************************************/
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#ifndef __HC32F460_SRAM_H__
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#define __HC32F460_SRAM_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_SRAM_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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* \defgroup SramGroup Internal SRAM
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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///< SRAM wait cycle register, parity/ECC check register protect code definition
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#define SRAM_PROTECT_CODE (0x0000003Bu)
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/*******************************************************************************
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Start addr. End addr. Size Function
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SRAM1 0x20000000 0x2000FFFF 64KB Even Parity Check
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SRAM2 0x20010000 0x2001FFFF 64KB Even Parity Check
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SRAM3 0x20020000 0x20026FFF 28KB ECC Check
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SRAM_Ret 0x200F0000 0x200F0FFF 4KB Even Parity Check
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SRAM_HS 0x1FFF8000 0x1FFFFFFF 32KB Even Parity Check
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******************************************************************************/
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///< SRAM1 base address definition
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#define SRAM1_BASE_ADDR (*((volatile unsigned int*)(0x20000000UL)))
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///< SRAM2 base address definition
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#define SRAM2_BASE_ADDR (*((volatile unsigned int*)(0x20010000UL)))
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///< SRAM3 base address definition
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#define SRAM3_BASE_ADDR (*((volatile unsigned int*)(0x20020000UL)))
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///< Retention SRAM base address definition
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#define SRAMRET_BASE_ADDR (*((volatile unsigned int*)(0x200F0000UL)))
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///< High speed SRAM base address definition
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#define SRAMHS_BASE_ADDR (*((volatile unsigned int*)(0x1FFF8000UL)))
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typedef enum en_sram_index
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{
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Sram12Idx = 1u << 0,
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Sram3Idx = 1u << 1,
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SramHsIdx = 1u << 2,
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SramRetIdx = 1u << 3,
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}en_sram_index_t;
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/**
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*******************************************************************************
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** \brief Enumeration to the write/read cycles of SRAM
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**
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** \note
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******************************************************************************/
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typedef enum en_sram_rw_cycle
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{
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SramCycle1 = 0u,
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SramCycle2 = 1u,
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SramCycle3 = 2u,
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SramCycle4 = 3u,
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SramCycle5 = 4u,
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SramCycle6 = 5u,
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SramCycle7 = 6u,
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SramCycle8 = 7u,
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}en_sram_rw_cycle_t;
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/**
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*******************************************************************************
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** \brief Enumeration to ECC check mode
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**
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** \note
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******************************************************************************/
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typedef enum en_ecc_mode
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{
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EccMode0 = 0u, ///< disable ECC check function
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EccMode1 = 1u, ///< no 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected
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///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected
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EccMode2 = 2u, ///< generate 1 bit ECC flag, but no interrupt/reset if 1 bit-ECC is detected
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///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected
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EccMode3 = 3u, ///< generate 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected
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///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected
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}en_ecc_mode_t;
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/**
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*******************************************************************************
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** \brief Enumeration to operation after ECC/Parity error
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**
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** \note
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******************************************************************************/
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typedef enum en_ecc_py_err_op
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{
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SramNmi = 0u, ///< Generate NMI after ECC/Parity error detected
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SramReset = 1u, ///< Generate Reset after ECC/Parity error detected
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}en_ecc_py_err_op_t;
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/**
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*******************************************************************************
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** \brief Enumeration to the ECC/Parity error status of each SRAM
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**
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** \note
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******************************************************************************/
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typedef enum en_sram_err_status
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{
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Sram3EccErr1 = 1u << 0, ///< SRAM3 1 bit ECC error
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Sram3EccErr2 = 1u << 1, ///< SRAM3 2 bit ECC error
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Sram12ParityErr = 1u << 2, ///< SRAM1/2 parity error
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SramHSParityErr = 1u << 3, ///< High speed SRAM parity error
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SramRetParityErr = 1u << 4, ///< Retention SRAM parity error
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}en_sram_err_status_t;
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/**
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*******************************************************************************
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** \brief SRAM configuration
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**
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** \note The SRAM configuration structure
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******************************************************************************/
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typedef struct stc_sram_config
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{
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uint8_t u8SramIdx; ///< SRAM index, ref @ en_sram_index_t for details
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en_sram_rw_cycle_t enSramRC; ///< SRAM read wait cycle setting
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en_sram_rw_cycle_t enSramWC; ///< SRAM write wait cycle setting
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en_ecc_mode_t enSramEccMode; ///< SRAM ECC mode setting
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en_ecc_py_err_op_t enSramEccOp; ///< SRAM3 ECC error handling setting
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en_ecc_py_err_op_t enSramPyOp; ///< SRAM1/2/HS/Ret Parity error handling setting
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}stc_sram_config_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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* Global function prototypes (definition in C source)
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******************************************************************************/
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extern en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig);
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extern en_result_t SRAM_DeInit(void);
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extern en_result_t SRAM_WT_Disable(void);
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extern en_result_t SRAM_WT_Enable(void);
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extern en_result_t SRAM_CK_Disable(void);
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extern en_result_t SRAM_CK_Enable(void);
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extern en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus);
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extern en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus);
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//@} // SramGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* DDL_SRAM_ENABLE */
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#endif /* __HC32F460_SRAM_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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