2014-07-18 17:17:56 +08:00
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// startup_gcc.c - Startup code for use with GNU tools.
|
|
|
|
|
//
|
2017-04-25 18:02:51 +08:00
|
|
|
// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved.
|
2014-07-18 17:17:56 +08:00
|
|
|
// Software License Agreement
|
|
|
|
|
//
|
|
|
|
|
// Texas Instruments (TI) is supplying this software for use solely and
|
|
|
|
|
// exclusively on TI's microcontroller products. The software is owned by
|
|
|
|
|
// TI and/or its suppliers, and is protected under applicable copyright
|
|
|
|
|
// laws. You may not combine this software with "viral" open-source
|
|
|
|
|
// software in order to form a larger program.
|
|
|
|
|
//
|
|
|
|
|
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
|
|
|
|
|
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
|
|
|
|
|
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
|
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
|
|
|
|
|
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
|
|
|
|
|
// DAMAGES, FOR ANY REASON WHATSOEVER.
|
|
|
|
|
//
|
2017-04-25 18:02:51 +08:00
|
|
|
// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package.
|
2014-07-18 17:17:56 +08:00
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
|
|
|
|
|
#include <stdint.h>
|
|
|
|
|
#include "inc/hw_nvic.h"
|
|
|
|
|
#include "inc/hw_types.h"
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Forward declaration of the default fault handlers.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
void ResetISR(void);
|
|
|
|
|
static void NmiSR(void);
|
|
|
|
|
static void FaultISR(void);
|
|
|
|
|
static void IntDefaultHandler(void);
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The entry point for the application.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
extern int main(void);
|
|
|
|
|
|
|
|
|
|
extern void SysTick_Handler(void);
|
|
|
|
|
extern void PendSV_Handler(void);
|
2014-07-21 19:09:15 +08:00
|
|
|
extern void UART0_IRQHandler(void);
|
|
|
|
|
extern void HardFault_Handler(void);
|
2014-07-18 17:17:56 +08:00
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Reserve space for the system stack.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
static uint32_t pui32Stack[64];
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The vector table. Note that the proper constructs must be placed on this to
|
|
|
|
|
// ensure that it ends up at physical address 0x0000.0000.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
__attribute__ ((section(".isr_vector")))
|
|
|
|
|
void (* const g_pfnVectors[])(void) =
|
|
|
|
|
{
|
|
|
|
|
(void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)),
|
|
|
|
|
// The initial stack pointer
|
|
|
|
|
ResetISR, // The reset handler
|
|
|
|
|
NmiSR, // The NMI handler
|
2014-07-21 19:09:15 +08:00
|
|
|
HardFault_Handler, // The hard fault handler
|
2014-07-18 17:17:56 +08:00
|
|
|
IntDefaultHandler, // The MPU fault handler
|
|
|
|
|
IntDefaultHandler, // The bus fault handler
|
|
|
|
|
IntDefaultHandler, // The usage fault handler
|
|
|
|
|
0, // Reserved
|
|
|
|
|
0, // Reserved
|
|
|
|
|
0, // Reserved
|
|
|
|
|
0, // Reserved
|
|
|
|
|
IntDefaultHandler, // SVCall handler
|
|
|
|
|
IntDefaultHandler, // Debug monitor handler
|
|
|
|
|
0, // Reserved
|
|
|
|
|
PendSV_Handler, // The PendSV handler
|
|
|
|
|
SysTick_Handler, // The SysTick handler
|
|
|
|
|
IntDefaultHandler, // GPIO Port A
|
|
|
|
|
IntDefaultHandler, // GPIO Port B
|
|
|
|
|
IntDefaultHandler, // GPIO Port C
|
|
|
|
|
IntDefaultHandler, // GPIO Port D
|
|
|
|
|
IntDefaultHandler, // GPIO Port E
|
2014-07-21 19:09:15 +08:00
|
|
|
UART0_IRQHandler, // UART0 Rx and Tx
|
2014-07-18 17:17:56 +08:00
|
|
|
IntDefaultHandler, // UART1 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // SSI0 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // I2C0 Master and Slave
|
|
|
|
|
IntDefaultHandler, // PWM Fault
|
|
|
|
|
IntDefaultHandler, // PWM Generator 0
|
|
|
|
|
IntDefaultHandler, // PWM Generator 1
|
|
|
|
|
IntDefaultHandler, // PWM Generator 2
|
|
|
|
|
IntDefaultHandler, // Quadrature Encoder 0
|
|
|
|
|
IntDefaultHandler, // ADC Sequence 0
|
|
|
|
|
IntDefaultHandler, // ADC Sequence 1
|
|
|
|
|
IntDefaultHandler, // ADC Sequence 2
|
|
|
|
|
IntDefaultHandler, // ADC Sequence 3
|
|
|
|
|
IntDefaultHandler, // Watchdog timer
|
|
|
|
|
IntDefaultHandler, // Timer 0 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 0 subtimer B
|
|
|
|
|
IntDefaultHandler, // Timer 1 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 1 subtimer B
|
|
|
|
|
IntDefaultHandler, // Timer 2 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 2 subtimer B
|
|
|
|
|
IntDefaultHandler, // Analog Comparator 0
|
|
|
|
|
IntDefaultHandler, // Analog Comparator 1
|
|
|
|
|
IntDefaultHandler, // Analog Comparator 2
|
|
|
|
|
IntDefaultHandler, // System Control (PLL, OSC, BO)
|
|
|
|
|
IntDefaultHandler, // FLASH Control
|
|
|
|
|
IntDefaultHandler, // GPIO Port F
|
|
|
|
|
IntDefaultHandler, // GPIO Port G
|
|
|
|
|
IntDefaultHandler, // GPIO Port H
|
|
|
|
|
IntDefaultHandler, // UART2 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // SSI1 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // Timer 3 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 3 subtimer B
|
|
|
|
|
IntDefaultHandler, // I2C1 Master and Slave
|
|
|
|
|
IntDefaultHandler, // CAN0
|
|
|
|
|
IntDefaultHandler, // CAN1
|
|
|
|
|
IntDefaultHandler, // Ethernet
|
|
|
|
|
IntDefaultHandler, // Hibernate
|
|
|
|
|
IntDefaultHandler, // USB0
|
|
|
|
|
IntDefaultHandler, // PWM Generator 3
|
|
|
|
|
IntDefaultHandler, // uDMA Software Transfer
|
|
|
|
|
IntDefaultHandler, // uDMA Error
|
|
|
|
|
IntDefaultHandler, // ADC1 Sequence 0
|
|
|
|
|
IntDefaultHandler, // ADC1 Sequence 1
|
|
|
|
|
IntDefaultHandler, // ADC1 Sequence 2
|
|
|
|
|
IntDefaultHandler, // ADC1 Sequence 3
|
|
|
|
|
IntDefaultHandler, // External Bus Interface 0
|
|
|
|
|
IntDefaultHandler, // GPIO Port J
|
|
|
|
|
IntDefaultHandler, // GPIO Port K
|
|
|
|
|
IntDefaultHandler, // GPIO Port L
|
|
|
|
|
IntDefaultHandler, // SSI2 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // SSI3 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // UART3 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // UART4 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // UART5 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // UART6 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // UART7 Rx and Tx
|
|
|
|
|
IntDefaultHandler, // I2C2 Master and Slave
|
|
|
|
|
IntDefaultHandler, // I2C3 Master and Slave
|
|
|
|
|
IntDefaultHandler, // Timer 4 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 4 subtimer B
|
|
|
|
|
IntDefaultHandler, // Timer 5 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 5 subtimer B
|
|
|
|
|
IntDefaultHandler, // FPU
|
|
|
|
|
0, // Reserved
|
|
|
|
|
0, // Reserved
|
|
|
|
|
IntDefaultHandler, // I2C4 Master and Slave
|
|
|
|
|
IntDefaultHandler, // I2C5 Master and Slave
|
|
|
|
|
IntDefaultHandler, // GPIO Port M
|
|
|
|
|
IntDefaultHandler, // GPIO Port N
|
|
|
|
|
0, // Reserved
|
|
|
|
|
IntDefaultHandler, // Tamper
|
|
|
|
|
IntDefaultHandler, // GPIO Port P (Summary or P0)
|
|
|
|
|
IntDefaultHandler, // GPIO Port P1
|
|
|
|
|
IntDefaultHandler, // GPIO Port P2
|
|
|
|
|
IntDefaultHandler, // GPIO Port P3
|
|
|
|
|
IntDefaultHandler, // GPIO Port P4
|
|
|
|
|
IntDefaultHandler, // GPIO Port P5
|
|
|
|
|
IntDefaultHandler, // GPIO Port P6
|
|
|
|
|
IntDefaultHandler, // GPIO Port P7
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q (Summary or Q0)
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q1
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q2
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q3
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q4
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q5
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q6
|
|
|
|
|
IntDefaultHandler, // GPIO Port Q7
|
|
|
|
|
IntDefaultHandler, // GPIO Port R
|
|
|
|
|
IntDefaultHandler, // GPIO Port S
|
|
|
|
|
IntDefaultHandler, // SHA/MD5 0
|
|
|
|
|
IntDefaultHandler, // AES 0
|
|
|
|
|
IntDefaultHandler, // DES3DES 0
|
|
|
|
|
IntDefaultHandler, // LCD Controller 0
|
|
|
|
|
IntDefaultHandler, // Timer 6 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 6 subtimer B
|
|
|
|
|
IntDefaultHandler, // Timer 7 subtimer A
|
|
|
|
|
IntDefaultHandler, // Timer 7 subtimer B
|
|
|
|
|
IntDefaultHandler, // I2C6 Master and Slave
|
|
|
|
|
IntDefaultHandler, // I2C7 Master and Slave
|
|
|
|
|
IntDefaultHandler, // HIM Scan Matrix Keyboard 0
|
|
|
|
|
IntDefaultHandler, // One Wire 0
|
|
|
|
|
IntDefaultHandler, // HIM PS/2 0
|
|
|
|
|
IntDefaultHandler, // HIM LED Sequencer 0
|
|
|
|
|
IntDefaultHandler, // HIM Consumer IR 0
|
|
|
|
|
IntDefaultHandler, // I2C8 Master and Slave
|
|
|
|
|
IntDefaultHandler, // I2C9 Master and Slave
|
|
|
|
|
IntDefaultHandler // GPIO Port T
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are constructs created by the linker, indicating where the
|
|
|
|
|
// the "data" and "bss" segments reside in memory. The initializers for the
|
|
|
|
|
// for the "data" segment resides immediately following the "text" segment.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
2017-12-31 21:19:52 +08:00
|
|
|
extern uint32_t _sidata;
|
|
|
|
|
extern uint32_t _sdata;
|
2014-07-18 17:17:56 +08:00
|
|
|
extern uint32_t _edata;
|
2017-12-31 21:19:52 +08:00
|
|
|
extern uint32_t _sbss;
|
2014-07-18 17:17:56 +08:00
|
|
|
extern uint32_t _ebss;
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// This is the code that gets called when the processor first starts execution
|
|
|
|
|
// following a reset event. Only the absolutely necessary set is performed,
|
|
|
|
|
// after which the application supplied entry() routine is called. Any fancy
|
|
|
|
|
// actions (such as making decisions based on the reset cause register, and
|
|
|
|
|
// resetting the bits in that register) are left solely in the hands of the
|
|
|
|
|
// application.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
void
|
|
|
|
|
ResetISR(void)
|
|
|
|
|
{
|
|
|
|
|
uint32_t *pui32Src, *pui32Dest;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Copy the data segment initializers from flash to SRAM.
|
|
|
|
|
//
|
2017-12-31 21:19:52 +08:00
|
|
|
pui32Src = &_sidata;
|
|
|
|
|
for(pui32Dest = &_sdata; pui32Dest < &_edata; )
|
2014-07-18 17:17:56 +08:00
|
|
|
{
|
|
|
|
|
*pui32Dest++ = *pui32Src++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Zero fill the bss segment.
|
|
|
|
|
//
|
2017-12-31 21:19:52 +08:00
|
|
|
__asm(" ldr r0, =_sbss\n"
|
2014-07-18 17:17:56 +08:00
|
|
|
" ldr r1, =_ebss\n"
|
|
|
|
|
" mov r2, #0\n"
|
|
|
|
|
" .thumb_func\n"
|
|
|
|
|
"zero_loop:\n"
|
|
|
|
|
" cmp r0, r1\n"
|
|
|
|
|
" it lt\n"
|
|
|
|
|
" strlt r2, [r0], #4\n"
|
|
|
|
|
" blt zero_loop");
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Enable the floating-point unit. This must be done here to handle the
|
|
|
|
|
// case where main() uses floating-point and the function prologue saves
|
|
|
|
|
// floating-point registers (which will fault if floating-point is not
|
|
|
|
|
// enabled). Any configuration of the floating-point unit using DriverLib
|
|
|
|
|
// APIs must be done here prior to the floating-point unit being enabled.
|
|
|
|
|
//
|
|
|
|
|
// Note that this does not use DriverLib since it might not be included in
|
|
|
|
|
// this project.
|
|
|
|
|
//
|
|
|
|
|
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
|
|
|
|
|
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
|
|
|
|
|
NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Call the application's entry point.
|
|
|
|
|
//
|
|
|
|
|
main();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// This is the code that gets called when the processor receives a NMI. This
|
|
|
|
|
// simply enters an infinite loop, preserving the system state for examination
|
|
|
|
|
// by a debugger.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
static void
|
|
|
|
|
NmiSR(void)
|
|
|
|
|
{
|
|
|
|
|
//
|
|
|
|
|
// Enter an infinite loop.
|
|
|
|
|
//
|
|
|
|
|
while(1)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// This is the code that gets called when the processor receives a fault
|
|
|
|
|
// interrupt. This simply enters an infinite loop, preserving the system state
|
|
|
|
|
// for examination by a debugger.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
static void
|
|
|
|
|
FaultISR(void)
|
|
|
|
|
{
|
|
|
|
|
//
|
|
|
|
|
// Enter an infinite loop.
|
|
|
|
|
//
|
|
|
|
|
while(1)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// This is the code that gets called when the processor receives an unexpected
|
|
|
|
|
// interrupt. This simply enters an infinite loop, preserving the system state
|
|
|
|
|
// for examination by a debugger.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
static void
|
|
|
|
|
IntDefaultHandler(void)
|
|
|
|
|
{
|
|
|
|
|
//
|
|
|
|
|
// Go into an infinite loop.
|
|
|
|
|
//
|
|
|
|
|
while(1)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
}
|
