2013-01-08 22:40:58 +08:00
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/*
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* File : dm9000a.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-07-01 Bernard the first version
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*/
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#ifndef __DM9000_H__
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#define __DM9000_H__
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#define DM9000_IO_BASE 0x6C000000
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#define DM9000_DATA_BASE 0x6C000008
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#define DM9000_IO (*((volatile rt_uint16_t *) 0x6C000000)) // CMD = 0
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#define DM9000_DATA (*((volatile rt_uint16_t *) 0x6C000008)) // CMD = 1
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#define DM9000_inb(r) (*(volatile rt_uint8_t *)r)
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#define DM9000_outb(r, d) (*(volatile rt_uint8_t *)r = d)
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#define DM9000_inw(r) (*(volatile rt_uint16_t *)r)
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#define DM9000_outw(r, d) (*(volatile rt_uint16_t *)r = d)
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#define RST_1() GPIO_SetBits(GPIOE,GPIO_Pin_5)
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#define RST_0() GPIO_ResetBits(GPIOE,GPIO_Pin_5)
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#define DM9000_ID 0x90000A46 /* DM9000 ID */
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#define DM9000_PKT_MAX 1536 /* Received packet max size */
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#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
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#define DM9000_NCR 0x00
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#define DM9000_NSR 0x01
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#define DM9000_TCR 0x02
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#define DM9000_TSR1 0x03
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#define DM9000_TSR2 0x04
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#define DM9000_RCR 0x05
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#define DM9000_RSR 0x06
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#define DM9000_ROCR 0x07
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#define DM9000_BPTR 0x08
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#define DM9000_FCTR 0x09
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#define DM9000_FCR 0x0A
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#define DM9000_EPCR 0x0B
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#define DM9000_EPAR 0x0C
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#define DM9000_EPDRL 0x0D
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#define DM9000_EPDRH 0x0E
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#define DM9000_WCR 0x0F
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#define DM9000_PAR 0x10
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#define DM9000_MAR 0x16
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#define DM9000_GPCR 0x1e
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#define DM9000_GPR 0x1f
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#define DM9000_TRPAL 0x22
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#define DM9000_TRPAH 0x23
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#define DM9000_RWPAL 0x24
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#define DM9000_RWPAH 0x25
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#define DM9000_VIDL 0x28
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#define DM9000_VIDH 0x29
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#define DM9000_PIDL 0x2A
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#define DM9000_PIDH 0x2B
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#define DM9000_CHIPR 0x2C
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#define DM9000_TCR2 0x2D
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#define DM9000_OTCR 0x2E
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#define DM9000_SMCR 0x2F
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#define DM9000_ETCR 0x30 /* early transmit control/status register */
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#define DM9000_CSCR 0x31 /* check sum control register */
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#define DM9000_RCSSR 0x32 /* receive check sum status register */
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#define DM9000_MRCMDX 0xF0
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#define DM9000_MRCMD 0xF2
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#define DM9000_MRRL 0xF4
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#define DM9000_MRRH 0xF5
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#define DM9000_MWCMDX 0xF6
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#define DM9000_MWCMD 0xF8
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#define DM9000_MWRL 0xFA
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#define DM9000_MWRH 0xFB
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#define DM9000_TXPLL 0xFC
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#define DM9000_TXPLH 0xFD
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#define DM9000_ISR 0xFE
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#define DM9000_IMR 0xFF
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#define CHIPR_DM9000A 0x19
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#define CHIPR_DM9000B 0x1B
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#define NCR_EXT_PHY (1<<7)
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#define NCR_WAKEEN (1<<6)
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#define NCR_FCOL (1<<4)
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#define NCR_FDX (1<<3)
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#define NCR_LBK (3<<1)
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#define NCR_RST (1<<0)
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#define NSR_SPEED (1<<7)
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#define NSR_LINKST (1<<6)
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#define NSR_WAKEST (1<<5)
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#define NSR_TX2END (1<<3)
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#define NSR_TX1END (1<<2)
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#define NSR_RXOV (1<<1)
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#define TCR_TJDIS (1<<6)
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#define TCR_EXCECM (1<<5)
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#define TCR_PAD_DIS2 (1<<4)
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#define TCR_CRC_DIS2 (1<<3)
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#define TCR_PAD_DIS1 (1<<2)
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#define TCR_CRC_DIS1 (1<<1)
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#define TCR_TXREQ (1<<0)
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#define TSR_TJTO (1<<7)
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#define TSR_LC (1<<6)
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#define TSR_NC (1<<5)
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#define TSR_LCOL (1<<4)
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#define TSR_COL (1<<3)
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#define TSR_EC (1<<2)
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#define RCR_WTDIS (1<<6)
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#define RCR_DIS_LONG (1<<5)
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#define RCR_DIS_CRC (1<<4)
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#define RCR_ALL (1<<3)
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#define RCR_RUNT (1<<2)
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#define RCR_PRMSC (1<<1)
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#define RCR_RXEN (1<<0)
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#define RSR_RF (1<<7)
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#define RSR_MF (1<<6)
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#define RSR_LCS (1<<5)
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#define RSR_RWTO (1<<4)
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#define RSR_PLE (1<<3)
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#define RSR_AE (1<<2)
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#define RSR_CE (1<<1)
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#define RSR_FOE (1<<0)
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#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
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#define FCTR_LWOT(ot) ( ot & 0xf )
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#define IMR_PAR (1<<7)
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#define IMR_ROOM (1<<3)
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#define IMR_ROM (1<<2)
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#define IMR_PTM (1<<1)
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#define IMR_PRM (1<<0)
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#define ISR_ROOS (1<<3)
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#define ISR_ROS (1<<2)
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#define ISR_PTS (1<<1)
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#define ISR_PRS (1<<0)
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#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
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#define EPCR_REEP (1<<5)
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#define EPCR_WEP (1<<4)
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#define EPCR_EPOS (1<<3)
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#define EPCR_ERPRR (1<<2)
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#define EPCR_ERPRW (1<<1)
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#define EPCR_ERRE (1<<0)
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#define GPCR_GEP_CNTL (1<<0)
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void rt_hw_dm9000_init(void);
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#endif
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