125 lines
5.9 KiB
C
125 lines
5.9 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file hal_fsmc.c
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/// @author AE TEAM
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/// @brief THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS.
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/// Interface with SRAM, PSRAM, NOR memories
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/// Interrupts and flags management
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#define _HAL_FSMC_C_
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// Files includes
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#include "reg_rcc.h"
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#include "reg_syscfg.h"
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#include "hal_fsmc.h"
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup MM32_Hardware_Abstract_Layer
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup FSMC_HAL
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup FSMC_Exported_Functions
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/// @{
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void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct)
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{
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init_struct->FSMC_Mode = FSMC_Mode_NorFlash;
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init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX;
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init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0;
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init_struct->FSMC_MemSize = FSMC_MemSize_64MB;
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init_struct->FSMC_MemType = FSMC_MemType_NorSRAM;
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}
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void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct)
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{
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init_struct->FSMC_SMReadPipe = 0;
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init_struct->FSMC_ReadyMode = 0;
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init_struct->FSMC_WritePeriod = 0x2;
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init_struct->FSMC_WriteHoldTime = 1;
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init_struct->FSMC_AddrSetTime = 3;
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init_struct->FSMC_ReadPeriod = 0x1;
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init_struct->FSMC_DataWidth = FSMC_DataWidth_16bits;
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}
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void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct)
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{
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SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN);
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SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \
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(u32)init_struct->FSMC_AddrDataMode;
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FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \
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(u32)init_struct->FSMC_MemSize | \
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(u32)init_struct->FSMC_MemType;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Initialize the FSMC_NORSRAM Timing according to the specified
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/// parameters in the FSMC_NORSRAM_TimingTypeDef
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/// @param FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure
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/// @param Bank: NORSRAM bank number
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank)
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{
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// Set FSMC_NORSRAM device timing parameters
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if(bank == FSMC_NORSRAM_BANK0) {
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FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
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FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0;
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FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos;
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}
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else if(bank == FSMC_NORSRAM_BANK1) {
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FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
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FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1;
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FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos;
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}
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else if(bank == FSMC_NORSRAM_BANK2) {
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FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
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(u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
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FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2;
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FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos;
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}
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}
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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