100 lines
2.1 KiB
C
100 lines
2.1 KiB
C
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/*
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* Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-16 Dystopia the first version
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*/
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#ifndef __BM3803_H__
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#define __BM3803_H__
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struct lregs
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{
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/* address = 0x80000000 */
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unsigned int memcfg1; /* 0x00 */
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unsigned int memcfg2;
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unsigned int memcfg3;
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unsigned int failaddr;
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unsigned int memstatus; /* 0x10 */
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unsigned int cachectrl;
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unsigned int powerdown;
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unsigned int writeprot1;
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unsigned int writeprot2; /* 0x20 */
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unsigned int pcr;
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unsigned int dummy2;
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unsigned int dummy3;
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unsigned int dummy4; /* 0x30 */
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unsigned int dummy5;
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unsigned int dummy6;
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unsigned int dummy7;
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unsigned int timercnt1; /* 0x40 */
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unsigned int timerload1;
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unsigned int timerctrl1;
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unsigned int wdog;
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unsigned int timercnt2; /* 0x50 */
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unsigned int timerload2;
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unsigned int timerctrl2;
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unsigned int dummy8;
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unsigned int scalercnt; /* 0x60 */
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unsigned int scalerload;
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unsigned int dummy9;
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unsigned int dummy10;
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unsigned int uartdata1; /* 0x70 */
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unsigned int uartstatus1;
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unsigned int uartctrl1;
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unsigned int uartscaler1;
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unsigned int uartdata2; /* 0x80 */
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unsigned int uartstatus2;
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unsigned int uartctrl2;
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unsigned int uartscaler2;
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unsigned int irqmask; /* 0x90 */
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unsigned int irqpend;
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unsigned int irqforce;
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unsigned int irqclear;
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unsigned int piodata; /* 0xA0 */
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unsigned int piodir;
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unsigned int pioirq;
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unsigned int dummy11;
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unsigned int imask2; /* 0xB0 */
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unsigned int ipend2;
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unsigned int istat2;
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unsigned int dummy12;
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unsigned int dummy13; /* 0xC0 */
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unsigned int dcomstatus;
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unsigned int dcomctrl;
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unsigned int dcomscaler;
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unsigned int dummy14; /* 0xD0 */
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unsigned int dummy15;
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unsigned int dummy16;
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unsigned int dummy17;
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unsigned int uartdata3; /* 0xE0 */
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unsigned int uartstatus3;
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unsigned int uartctrl3;
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unsigned int uartscaler3;
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};
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#define PREGS 0x80000000
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#define UART1_BASE (PREGS + 0x70)
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#define TIMER2_TT 0x19
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#define UART1_TT 0x13
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#endif
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