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rt-thread/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c

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[bsp]add swm320-lq100 bsp
2018-12-24 17:17:27 +08:00
/******************************************************************************************************************************************
* <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SWM320_timr.c
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: SWM320<EFBFBD><EFBFBD>Ƭ<EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><EFBFBD>: http://www.synwit.com.cn/e/tool/gbook/?bid=1
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
* <EFBFBD>汾<EFBFBD><EFBFBD><EFBFBD><EFBFBD>: V1.1.0 2017<EFBFBD><EFBFBD>10<EFBFBD><EFBFBD>25<EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼:
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_timr.h"
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_Init()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: TIMR<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>/<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* uint32_t mode TIMR_MODE_TIMER <EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ģʽ TIMR_MODE_COUNTER <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
* uint32_t period <EFBFBD><EFBFBD>ʱ/<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* uint32_t int_en <EFBFBD>ж<EFBFBD>ʹ<EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en)
{
SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos);
TIMR_Stop(TIMRx); //һЩ<D2BB>ؼ<EFBFBD><D8BC>Ĵ<EFBFBD><C4B4><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD>ڶ<EFBFBD>ʱ<EFBFBD><CAB1>ֹͣʱ<D6B9><CAB1><EFBFBD><EFBFBD>
TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk;
TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos;
TIMRx->LDVAL = period;
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //ʹ<><CAB9><EFBFBD>ж<EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־
TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos);
if (int_en) NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
TIMRG->IF = (1 << TIMRG_IF_TIMR1_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos);
if (int_en) NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
TIMRG->IF = (1 << TIMRG_IF_TIMR2_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos);
if (int_en) NVIC_EnableIRQ(TIMR2_IRQn);
break;
case ((uint32_t)TIMR3):
TIMRG->IF = (1 << TIMRG_IF_TIMR3_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos);
if (int_en) NVIC_EnableIRQ(TIMR3_IRQn);
break;
case ((uint32_t)TIMR4):
TIMRG->IF = (1 << TIMRG_IF_TIMR4_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos);
if (int_en) NVIC_EnableIRQ(TIMR4_IRQn);
break;
case ((uint32_t)TIMR5):
TIMRG->IF = (1 << TIMRG_IF_TIMR5_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos);
if (int_en) NVIC_EnableIRQ(TIMR5_IRQn);
break;
}
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_Start()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD>ʼֵ<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ʱ/<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_Start(TIMR_TypeDef *TIMRx)
{
TIMRx->CTRL |= TIMR_CTRL_EN_Msk;
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_Stop()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: ֹͣ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_Stop(TIMR_TypeDef *TIMRx)
{
TIMRx->CTRL &= ~TIMR_CTRL_EN_Msk;
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_Halt()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ͣ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD><EFBFBD>ֲ<EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_Halt(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_Resume()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD>ָ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_Resume(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_SetPeriod()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD>ʱ/<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* uint32_t period <EFBFBD><EFBFBD>ʱ/<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period)
{
TIMRx->LDVAL = period;
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_GetPeriod()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD>ʱ/<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: uint32_t <EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD>ʱ/<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx)
{
return TIMRx->LDVAL;
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_GetCurValue()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: uint32_t <EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx)
{
return TIMRx->CVAL;
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_INTEn()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: ʹ<EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_INTEn(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR0_Pos);
NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR1_Pos);
NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR2_Pos);
NVIC_EnableIRQ(TIMR2_IRQn);
break;
case ((uint32_t)TIMR3):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR3_Pos);
NVIC_EnableIRQ(TIMR3_IRQn);
break;
case ((uint32_t)TIMR4):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR4_Pos);
NVIC_EnableIRQ(TIMR4_IRQn);
break;
case ((uint32_t)TIMR5):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR5_Pos);
NVIC_EnableIRQ(TIMR5_IRQn);
break;
}
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_INTDis()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_INTDis(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_INTClr()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<EFBFBD>־
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
void TIMR_INTClr(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: TIMR_INTStat()
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ȡ<EFBFBD>ж<EFBFBD>״̬
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: TIMR_TypeDef * TIMRx ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĶ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TIMR0<EFBFBD><EFBFBD>TIMR1<EFBFBD><EFBFBD>TIMR2<EFBFBD><EFBFBD>TIMR3<EFBFBD><EFBFBD>TIMR4<EFBFBD><EFBFBD>TIMR5
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: uint32_t 0 TIMRxδ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> 1 TIMRx<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
******************************************************************************************************************************************/
uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
return (TIMRG->IF & TIMRG_IF_TIMR0_Msk) ? 1 : 0;
case ((uint32_t)TIMR1):
return (TIMRG->IF & TIMRG_IF_TIMR1_Msk) ? 1 : 0;
case ((uint32_t)TIMR2):
return (TIMRG->IF & TIMRG_IF_TIMR2_Msk) ? 1 : 0;
case ((uint32_t)TIMR3):
return (TIMRG->IF & TIMRG_IF_TIMR3_Msk) ? 1 : 0;
case ((uint32_t)TIMR4):
return (TIMRG->IF & TIMRG_IF_TIMR4_Msk) ? 1 : 0;
case ((uint32_t)TIMR5):
return (TIMRG->IF & TIMRG_IF_TIMR5_Msk) ? 1 : 0;
}
return 0;
}