2009-07-03 07:18:14 +08:00
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.extern main /* <20><><EFBFBD><EFBFBD><EFBFBD>ⲿC<E2B2BF><43><EFBFBD><EFBFBD> */
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.extern rt_interrupt_enter
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.extern rt_interrupt_leave
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2011-09-19 12:40:50 +08:00
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.extern rt_thread_switch_interrupt_flag
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2009-07-03 07:18:14 +08:00
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.extern rt_interrupt_from_thread
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.extern rt_interrupt_to_thread
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.extern rt_hw_trap_irq
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.global start
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.global endless_loop
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.global rt_hw_context_switch_interrupt_do
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/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
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.set MODE_USR, 0x10 /* User Mode */
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.set MODE_FIQ, 0x11 /* FIQ Mode */
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.set MODE_IRQ, 0x12 /* IRQ Mode */
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.set MODE_SVC, 0x13 /* Supervisor Mode */
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.set MODE_ABT, 0x17 /* Abort Mode */
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.set MODE_UND, 0x1B /* Undefined Mode */
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.set MODE_SYS, 0x1F /* System Mode */
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.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
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.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
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/* VPBDIV definitions*/
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.equ VPBDIV, 0xE01FC100
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.set VPBDIV_VALUE, 0x00000000
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/* Phase Locked Loop (PLL) definitions*/
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2011-07-02 23:16:11 +08:00
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.equ PLL_BASE, 0xE01FC080 /* PLL Base Address */
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.equ PLLCON_OFS, 0x00 /* PLL Control Offset */
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.equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */
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.equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */
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.equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */
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.equ PLLCON_PLLE, (1<<0) /* PLL Enable */
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.equ PLLCON_PLLC, (1<<1) /* PLL Connect */
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.equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */
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.equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */
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.equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */
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.equ PLLCFG_Val, 0x00000024 /* <o1.0..4> MSEL: PLL Multiplier Selection,<o1.5..6> PSEL: PLL Divider Selection */
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2009-07-03 07:18:14 +08:00
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.equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/
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/* Memory Accelerator Module (MAM) definitions*/
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.equ MAM_BASE, 0xE01FC000
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.equ MAMCR_OFS, 0x00
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.equ MAMTIM_OFS, 0x04
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.equ MAMCR_Val, 0x00000002
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.equ MAMTIM_Val, 0x00000004
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.equ VICIntEnClr, 0xFFFFF014
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.equ VICIntSelect, 0xFFFFF00C
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/************* Ŀ<><C4BF><EFBFBD><EFBFBD><EFBFBD>ý<EFBFBD><C3BD><EFBFBD> *************/
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/* Setup the operating mode & stack.*/
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/* --------------------------------- */
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2011-07-02 23:16:11 +08:00
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.global _reset
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2009-07-03 07:18:14 +08:00
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_reset:
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.code 32
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.align 0
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/************************* PLL_SETUP **********************************/
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ldr r0, =PLL_BASE
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mov r1, #0xAA
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mov r2, #0x55
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/* Configure and Enable PLL */
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mov r3, #PLLCFG_Val
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str r3, [r0, #PLLCFG_OFS]
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mov r3, #PLLCON_PLLE
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str r3, [r0, #PLLCON_OFS]
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str r1, [r0, #PLLFEED_OFS]
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str r2, [r0, #PLLFEED_OFS]
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/* Wait until PLL Locked */
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PLL_Locked_loop:
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ldr r3, [r0, #PLLSTAT_OFS]
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2011-07-02 23:16:11 +08:00
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ands r3, r3, #PLLSTAT_PLOCK
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2009-07-03 07:18:14 +08:00
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beq PLL_Locked_loop
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/* Switch to PLL Clock */
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mov r3, #(PLLCON_PLLE|PLLCON_PLLC)
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str r3, [r0, #PLLCON_OFS]
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str r1, [r0, #PLLFEED_OFS]
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str R2, [r0, #PLLFEED_OFS]
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/************************* PLL_SETUP **********************************/
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/************************ Setup VPBDIV ********************************/
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ldr r0, =VPBDIV
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ldr r1, =VPBDIV_VALUE
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str r1, [r0]
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/************************ Setup VPBDIV ********************************/
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/************** Setup MAM **************/
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ldr r0, =MAM_BASE
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mov r1, #MAMTIM_Val
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str r1, [r0, #MAMTIM_OFS]
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mov r1, #MAMCR_Val
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str r1, [r0, #MAMCR_OFS]
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/************** Setup MAM **************/
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/************************ setup stack *********************************/
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2011-07-02 23:16:11 +08:00
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ldr r0, .undefined_stack_top
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sub r0, r0, #4
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2009-07-03 07:18:14 +08:00
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msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
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mov sp, r0
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2011-07-02 23:16:11 +08:00
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ldr r0, .abort_stack_top
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sub r0, r0, #4
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2009-07-03 07:18:14 +08:00
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msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
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mov sp, r0
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2011-07-02 23:16:11 +08:00
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ldr r0, .fiq_stack_top
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sub r0, r0, #4
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2009-07-03 07:18:14 +08:00
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msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
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mov sp, r0
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2011-07-02 23:16:11 +08:00
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ldr r0, .irq_stack_top
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sub r0, r0, #4
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2009-07-03 07:18:14 +08:00
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msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
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mov sp, r0
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2011-07-02 23:16:11 +08:00
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ldr r0, .svc_stack_top
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sub r0, r0, #4
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2009-07-03 07:18:14 +08:00
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msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
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mov sp, r0
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/************************ setup stack ********************************/
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2011-07-02 23:16:11 +08:00
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/* copy .data to SRAM */
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ldr r1, =_sidata /* .data start in image */
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ldr r2, =_edata /* .data end in image */
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ldr r3, =_sdata /* sram data start */
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data_loop:
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ldr r0, [r1, #0]
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str r0, [r3]
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add r1, r1, #4
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add r3, r3, #4
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cmp r3, r2 /* check if data to clear */
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blo data_loop /* loop until done */
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* enter C code */
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2009-07-03 07:18:14 +08:00
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bl main
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.align 0
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2011-07-02 23:16:11 +08:00
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.undefined_stack_top:
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.word _undefined_stack_top
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.abort_stack_top:
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.word _abort_stack_top
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.fiq_stack_top:
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.word _fiq_stack_top
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.irq_stack_top:
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.word _irq_stack_top
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.svc_stack_top:
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.word _svc_stack_top
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2009-07-03 07:18:14 +08:00
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/*********************** END Clear BSS ******************************/
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2011-07-02 23:16:11 +08:00
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.section .init,"ax"
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.code 32
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.align 0
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.globl _start
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_start:
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2009-07-03 07:18:14 +08:00
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ldr pc, __start /* reset - _start */
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ldr pc, _undf /* undefined - _undf */
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ldr pc, _swi /* SWI - _swi */
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ldr pc, _pabt /* program abort - _pabt */
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ldr pc, _dabt /* data abort - _dabt */
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2011-07-02 23:16:11 +08:00
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.word 0xB8A06F58 /* reserved */
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2009-07-03 07:18:14 +08:00
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ldr pc, __IRQ_Handler /* IRQ - read the VIC */
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ldr pc, _fiq /* FIQ - _fiq */
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2011-07-02 23:16:11 +08:00
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__start:.word _reset
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2009-07-03 07:18:14 +08:00
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_undf: .word __undf /* undefined */
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_swi: .word __swi /* SWI */
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_pabt: .word __pabt /* program abort */
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_dabt: .word __dabt /* data abort */
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temp1: .word 0
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__IRQ_Handler: .word IRQ_Handler
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_fiq: .word __fiq /* FIQ */
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__undf: b . /* undefined */
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__swi : b .
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__pabt: b . /* program abort */
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__dabt: b . /* data abort */
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__fiq : b . /* FIQ */
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/* IRQ<52><51><EFBFBD><EFBFBD> */
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IRQ_Handler :
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stmfd sp!, {r0-r12,lr} /* <EFBFBD><EFBFBD>R0 <EFBFBD>C R12<EFBFBD><EFBFBD>LR<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>ѹջ */
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bl rt_interrupt_enter /* ֪ͨRT-Thread<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ģʽ */
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bl rt_hw_trap_irq /* <EFBFBD><EFBFBD>Ӧ<EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̴<EFBFBD><EFBFBD><EFBFBD> */
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bl rt_interrupt_leave /* ; ֪ͨRT-ThreadҪ<64>뿪<EFBFBD>ж<EFBFBD>ģʽ */
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2011-09-19 12:40:50 +08:00
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>rt_thread_switch_interrupt_flag<61><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>е<EFBFBD><D0B5>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
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ldr r0, =rt_thread_switch_interrupt_flag
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2009-07-03 07:18:14 +08:00
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ldr r1, [r0]
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cmp r1, #1
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beq rt_hw_context_switch_interrupt_do /* <EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD>ˣ<EFBFBD><CBA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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ldmfd sp!, {r0-r12,lr} /* <EFBFBD>ָ<EFBFBD>ջ */
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subs pc, lr, #4 /* <EFBFBD><EFBFBD>IRQ<EFBFBD>з<EFBFBD><EFBFBD><EFBFBD> */
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/*
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* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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* <EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>
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*/
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rt_hw_context_switch_interrupt_do:
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mov r1, #0 /* clear flag */
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/* <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD>־ */
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str r1, [r0] /* */
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ldmfd sp!, {r0-r12,lr}/* reload saved registers */
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/* <20>Ȼָ<C8BB><D6B8><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>̵߳<DFB3><CCB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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stmfd sp!, {r0-r3} /* save r0-r3 */
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/* <20><>R0 <20>C R3ѹջ<D1B9><D5BB><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD> */
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mov r1, sp /* <EFBFBD>Ѵ˴<EFBFBD><EFBFBD><EFBFBD>ջֵ<EFBFBD><EFBFBD><EFBFBD>浽R1 */
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add sp, sp, #16 /* restore sp */
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/* <20>ָ<EFBFBD>IRQ<52><51>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IRQģʽ */
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sub r2, lr, #4 /* save old task's pc to r2 */
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/* <20><><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD>̵߳<DFB3>PC<50><43>R2 */
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mrs r3, spsr /* disable interrupt <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ǰ<EFBFBD><EFBFBD>CPSR<EFBFBD><EFBFBD>R3<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD> */
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/* <20><><EFBFBD><EFBFBD>SPSR<53>Ĵ<EFBFBD><C4B4><EFBFBD>ֵ */
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orr r0, r3, #I_BIT|F_BIT
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msr spsr_c, r0 /* <EFBFBD>ر<EFBFBD>SPSR<EFBFBD>е<EFBFBD>IRQ/FIQ<EFBFBD>ж<EFBFBD> */
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ldr r0, =.+8 /* <EFBFBD>ѵ<EFBFBD>ǰ<EFBFBD><EFBFBD>ַ+8<EFBFBD><EFBFBD><EFBFBD>뵽R0<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> switch to interrupted task's stack */
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movs pc, r0 /* <EFBFBD>˳<EFBFBD>IRQģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPSR<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>óɹ<EFBFBD><EFBFBD>ж<EFBFBD>ģʽ */
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/* <EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD>IRQ<EFBFBD><EFBFBD><EFBFBD>غ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϲ<EFBFBD>û<EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>
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; R0<52>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>е<EFBFBD>λ<EFBFBD><CEBB>ʵ<EFBFBD>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>ָ<EFBFBD>
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; <20><>PC<50><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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; <20><>ʱ
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; ģʽ<C4A3>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ǰ<EFBFBD><C7B0>SVCģʽ<C4A3><CABD>
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; SP<53>Ĵ<EFBFBD><C4B4><EFBFBD>Ҳ<EFBFBD><D2B2>SVCģʽ<C4A3>µ<EFBFBD>ջ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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; R1<52><31><EFBFBD><EFBFBD>IRQģʽ<C4A3>µ<EFBFBD>ջָ<D5BB><D6B8>
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; R2<52><32><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD>̵߳<DFB3>PC
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; R3<52><33><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD>̵߳<DFB3>CPSR */
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stmfd sp!, {r2} /* push old task's pc */
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/* <20><><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PC */
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stmfd sp!, {r4-r12,lr}/* push old task's lr,r12-r4 */
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/* <20><><EFBFBD><EFBFBD>R4 <20>C R12<31><32>LR<4C>Ĵ<EFBFBD><C4B4><EFBFBD> */
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mov r4, r1 /* Special optimised code below */
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/* R1<52><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹջR0 <20>C R3<52><33><EFBFBD><EFBFBD>ջλ<D5BB><CEBB> */
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mov r5, r3 /* R3<EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD>̵߳<EFBFBD>CPSR */
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ldmfd r4!, {r0-r3} /* <EFBFBD>ָ<EFBFBD>R0 <EFBFBD>C R3 */
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stmfd sp!, {r0-r3} /* push old task's r3-r0 */
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/* R0 <20>C R3ѹջ<D1B9><D5BB><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD>߳<EFBFBD> */
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stmfd sp!, {r5} /* push old task's psr */
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/* <20>л<EFBFBD><D0BB><EFBFBD><EFBFBD>߳<EFBFBD>CPSRѹջ */
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mrs r4, spsr
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stmfd sp!, {r4} /* push old task's spsr */
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/* <20>л<EFBFBD><D0BB><EFBFBD><EFBFBD>߳<EFBFBD>SPSRѹջ */
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] /* store sp in preempted tasks's TCB */
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/* <20><><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD>̵߳<DFB3>SPָ<50><D6B8> */
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] /* get new task's stack pointer */
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/* <20><><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD>̵߳<DFB3>ջ */
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ldmfd sp!, {r4} /* pop new task's spsr */
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/* <20>ָ<EFBFBD>SPSR */
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msr SPSR_cxsf, r4
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ldmfd sp!, {r4} /* pop new task's psr */
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/* <20>ָ<EFBFBD>CPSR */
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msr CPSR_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
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/* <20>ָ<EFBFBD>R0 <20>C R12<31><32>LR<4C><52>PC<50>Ĵ<EFBFBD><C4B4><EFBFBD> */
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܹ<EFBFBD><DCB9><EFBFBD> */
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#if defined(CODE_PROTECTION)
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.org 0x01FC
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.word 0x87654321
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#endif
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