232 lines
9.7 KiB
C
232 lines
9.7 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright (c) 2016, NXP
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_RESET_H_
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#define _FSL_RESET_H_
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "fsl_device_registers.h"
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/*!
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* @addtogroup ksdk_common
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief reset driver version 2.0.0. */
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#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/*!
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* @brief Enumeration for peripheral reset control bits
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*
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* Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
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*/
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typedef enum _SYSCON_RSTn
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{
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kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
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kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
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kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */
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kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
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kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
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kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
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kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
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kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
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kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
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kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
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kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
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kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
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kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
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kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
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kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
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kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
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kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
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kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
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kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
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kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
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kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
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kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
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kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
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kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */
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kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */
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kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */
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kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */
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kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */
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kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
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kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
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} SYSCON_RSTn_t;
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/** Array initializers with peripheral reset bits **/
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#define ADC_RSTS \
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{ \
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kADC0_RST_SHIFT_RSTn \
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} /* Reset bits for ADC peripheral */
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#define CRC_RSTS \
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{ \
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kCRC_RST_SHIFT_RSTn \
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} /* Reset bits for CRC peripheral */
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#define DMA_RSTS \
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{ \
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kDMA_RST_SHIFT_RSTn \
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} /* Reset bits for DMA peripheral */
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#define DMIC_RSTS \
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{ \
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kDMIC_RST_SHIFT_RSTn \
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} /* Reset bits for ADC peripheral */
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#define FLEXCOMM_RSTS \
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{ \
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kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
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kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \
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} /* Reset bits for FLEXCOMM peripheral */
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#define GINT_RSTS \
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{ \
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kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
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} /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
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#define GPIO_RSTS \
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{ \
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kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
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} /* Reset bits for GPIO peripheral */
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#define INPUTMUX_RSTS \
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{ \
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kMUX_RST_SHIFT_RSTn \
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} /* Reset bits for INPUTMUX peripheral */
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#define IOCON_RSTS \
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{ \
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kIOCON_RST_SHIFT_RSTn \
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} /* Reset bits for IOCON peripheral */
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#define FLASH_RSTS \
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{ \
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kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
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} /* Reset bits for Flash peripheral */
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#define MRT_RSTS \
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{ \
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kMRT_RST_SHIFT_RSTn \
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} /* Reset bits for MRT peripheral */
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#define PINT_RSTS \
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{ \
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kPINT_RST_SHIFT_RSTn \
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} /* Reset bits for PINT peripheral */
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#define SCT_RSTS \
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{ \
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kSCT0_RST_SHIFT_RSTn \
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} /* Reset bits for SCT peripheral */
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#define CTIMER_RSTS \
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{ \
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kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
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kCT32B4_RST_SHIFT_RSTn \
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} /* Reset bits for TIMER peripheral */
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#define USB_RSTS \
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{ \
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kUSB_RST_SHIFT_RSTn \
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} /* Reset bits for USB peripheral */
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#define UTICK_RSTS \
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{ \
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kUTICK_RST_SHIFT_RSTn \
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} /* Reset bits for UTICK peripheral */
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#define WWDT_RSTS \
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{ \
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kWWDT_RST_SHIFT_RSTn \
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} /* Reset bits for WWDT peripheral */
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typedef SYSCON_RSTn_t reset_ip_name_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @brief Assert reset to peripheral.
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*
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* Asserts reset signal to specified peripheral module.
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*
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* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Clear reset to peripheral.
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*
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* Clears reset signal to specified peripheral module, allows it to operate.
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*
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* @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Reset peripheral module.
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*
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* Reset peripheral module.
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*
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* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_PeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Set slave core to reset state and hold.
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*/
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void RESET_SetSlaveCoreReset(void);
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/*!
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* @brief Release slave core from reset state.
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*/
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void RESET_ClearSlaveCoreReset(void);
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/*!
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* @brief Reset slave core with the boot entry.
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*/
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void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer);
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#if defined(__cplusplus)
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}
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#endif
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/*! @} */
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#endif /* _FSL_RESET_H_ */
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