533 lines
17 KiB
C
533 lines
17 KiB
C
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/*
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* File : drv_sdio.c
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-29 zdzn first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#include <string.h>
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#include "drv_sdio.h"
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#include "interrupt.h"
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#include "drv_gpio.h"
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#include "bcm283x.h"
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#include <drivers/mmcsd_core.h>
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#include "bcm283x.h"
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#include <rtdbg.h>
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#ifdef RT_USING_SDIO
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#define CONFIG_MMC_USE_DMA
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#define DMA_ALIGN (32U)
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typedef struct EMMCCommand
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{
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const char* name;
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unsigned int code;
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unsigned char resp;
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unsigned char rca;
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int delay;
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} EMMCCommand;
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static EMMCCommand sdCommandTable[] =
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{
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{"GO_IDLE_STATE", 0x00000000 | CMD_RSPNS_NO , RESP_NO , RCA_NO ,0},
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{"ALL_SEND_CID" , 0x02000000 | CMD_RSPNS_136 , RESP_R2I, RCA_NO ,0},
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{"SEND_REL_ADDR", 0x03000000 | CMD_RSPNS_48 , RESP_R6 , RCA_NO ,0},
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{"SET_DSR" , 0x04000000 | CMD_RSPNS_NO , RESP_NO , RCA_NO ,0},
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{"SWITCH_FUNC" , 0x06000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"CARD_SELECT" , 0x07000000 | CMD_RSPNS_48B , RESP_R1b, RCA_YES ,0},
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{"SEND_IF_COND" , 0x08000000 | CMD_RSPNS_48 , RESP_R7 , RCA_NO ,100},
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{"SEND_CSD" , 0x09000000 | CMD_RSPNS_136 , RESP_R2S, RCA_YES ,0},
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{"SEND_CID" , 0x0A000000 | CMD_RSPNS_136 , RESP_R2I, RCA_YES ,0},
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{"VOLT_SWITCH" , 0x0B000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"STOP_TRANS" , 0x0C000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0},
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{"SEND_STATUS" , 0x0D000000 | CMD_RSPNS_48 , RESP_R1 , RCA_YES ,0},
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{"GO_INACTIVE" , 0x0F000000 | CMD_RSPNS_NO , RESP_NO , RCA_YES ,0},
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{"SET_BLOCKLEN" , 0x10000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"READ_SINGLE" , 0x11000000 | CMD_RSPNS_48 | CMD_IS_DATA | TM_DAT_DIR_CH, RESP_R1 , RCA_NO ,0},
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{"READ_MULTI" , 0x12000000 | CMD_RSPNS_48 | TM_MULTI_DATA | TM_DAT_DIR_CH, RESP_R1 , RCA_NO ,0},
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{"SEND_TUNING" , 0x13000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"SPEED_CLASS" , 0x14000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0},
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{"SET_BLOCKCNT" , 0x17000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"WRITE_SINGLE" , 0x18000000 | CMD_RSPNS_48 | CMD_IS_DATA | TM_DAT_DIR_HC, RESP_R1 , RCA_NO ,0},
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{"WRITE_MULTI" , 0x19000000 | CMD_RSPNS_48 | TM_MULTI_DATA | TM_DAT_DIR_HC, RESP_R1 , RCA_NO ,0},
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{"PROGRAM_CSD" , 0x1B000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"SET_WRITE_PR" , 0x1C000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0},
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{"CLR_WRITE_PR" , 0x1D000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0},
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{"SND_WRITE_PR" , 0x1E000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"ERASE_WR_ST" , 0x20000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"ERASE_WR_END" , 0x21000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"ERASE" , 0x26000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0},
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{"LOCK_UNLOCK" , 0x2A000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"APP_CMD" , 0x37000000 | CMD_RSPNS_NO , RESP_NO , RCA_NO ,100},
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{"APP_CMD" , 0x37000000 | CMD_RSPNS_48 , RESP_R1 , RCA_YES ,0},
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{"GEN_CMD" , 0x38000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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// APP commands must be prefixed by an APP_CMD.
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{"SET_BUS_WIDTH", 0x06000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"SD_STATUS" , 0x0D000000 | CMD_RSPNS_48 , RESP_R1 , RCA_YES ,0}, // RCA???
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{"SEND_NUM_WRBL", 0x16000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"SEND_NUM_ERS" , 0x17000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"SD_SENDOPCOND", 0x29000000 | CMD_RSPNS_48 , RESP_R3 , RCA_NO ,1000},
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{"SET_CLR_DET" , 0x2A000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0},
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{"SEND_SCR" , 0x33000000 | CMD_RSPNS_48 | CMD_IS_DATA | TM_DAT_DIR_CH , RESP_R1 , RCA_NO ,0},
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};
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static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width);
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static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock);
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static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat);
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static inline rt_uint32_t read32(rt_uint32_t addr)
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{
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return( *((volatile rt_uint32_t *)(addr)) );
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}
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static inline void write32(rt_uint32_t addr, rt_uint32_t value)
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{
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*((volatile rt_uint32_t *)(addr)) = value;
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}
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static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd)
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{
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rt_uint32_t cmdidx;
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rt_uint32_t status;
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rt_err_t ret = RT_EOK;
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if(read32(pdat->virt + EMMC_STATUS) & SR_CMD_INHIBIT)
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write32(pdat->virt + EMMC_CMDTM, 0x0);
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EMMCCommand* cmdtab = &sdCommandTable[cmd->cmdidx];
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cmdidx = cmdtab->code;
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write32(pdat->virt + EMMC_ARG1, cmd->cmdarg);
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write32(pdat->virt + EMMC_CMDTM, cmdidx);
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do {
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status = read32(pdat->virt + EMMC_STATUS);
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} while(!(status & SR_CMD_INHIBIT));
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if(cmd->resptype & RESP_MASK)
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{
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cmd->response[0] = read32(pdat->virt + EMMC_RESP0);
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if(cmd->resptype & RESP_R2)
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{
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cmd->response[1] = read32(pdat->virt + EMMC_RESP1);
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cmd->response[2] = read32(pdat->virt + EMMC_RESP2);
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cmd->response[3] = read32(pdat->virt + EMMC_RESP3);
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}
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}
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return ret;
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}
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static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
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{
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rt_uint32_t * tmp = buf;
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rt_uint32_t count = blkcount * blksize;
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rt_uint32_t status, err;
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// status = read32(pdat->virt + PL180_STATUS);
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN);
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// while((!err) && (count >= sizeof(rt_uint32_t)))
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// {
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// if(status & PL180_STAT_RX_FIFO_AVL)
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// {
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// *(tmp) = read32(pdat->virt + PL180_FIFO);
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// tmp++;
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// count -= sizeof(rt_uint32_t);
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// }
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// status = read32(pdat->virt + PL180_STATUS);
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN);
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// }
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//
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN);
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// while(!err)
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// {
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// status = read32(pdat->virt + PL180_STATUS);
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN);
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// }
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//
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// if(status & PL180_STAT_DAT_TIME_OUT)
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// return -RT_ERROR;
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// else if (status & PL180_STAT_DAT_CRC_FAIL)
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// return -RT_ERROR;
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// else if (status & PL180_STAT_RX_OVERRUN)
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// return -RT_ERROR;
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// write32(pdat->virt + PL180_CLEAR, 0x1DC007FF);
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//
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// if(count)
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// return -RT_ERROR;
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return RT_EOK;
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}
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static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
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{
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rt_uint32_t * tmp = buf;
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rt_uint32_t count = blkcount * blksize;
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rt_uint32_t status, err;
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int i;
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// status = read32(pdat->virt + PL180_STATUS);
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT);
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// while(!err && count)
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// {
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// if(status & PL180_STAT_TX_FIFO_HALF)
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// {
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// if(count >= 8 * sizeof(rt_uint32_t))
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// {
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// for(i = 0; i < 8; i++)
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// write32(pdat->virt + PL180_FIFO, *(tmp + i));
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// tmp += 8;
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// count -= 8 * sizeof(rt_uint32_t);
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// }
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// else
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// {
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// while(count >= sizeof(rt_uint32_t))
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// {
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// write32(pdat->virt + PL180_FIFO, *tmp);
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// tmp++;
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// count -= sizeof(rt_uint32_t);
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// }
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// }
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// }
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// status = read32(pdat->virt + PL180_STATUS);
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT);
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// }
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//
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END);
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// while(!err)
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// {
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// status = read32(pdat->virt + PL180_STATUS);
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// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END);
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// }
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//
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// if(status & PL180_STAT_DAT_TIME_OUT)
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// return -RT_ERROR;
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// else if (status & PL180_STAT_DAT_CRC_FAIL)
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// return -RT_ERROR;
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// write32(pdat->virt + PL180_CLEAR, 0x1DC007FF);
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//
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// if(count)
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// return -RT_ERROR;
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return RT_EOK;
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}
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static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
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{
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rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz);
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rt_uint32_t blksz_bits = dat->blksz - 1;
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rt_err_t ret = -RT_ERROR;
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write32(pdat->virt + EMMC_BLKSIZECNT, dlen);
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if(dat->flag & DATA_DIR_READ)
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{
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write32(pdat->virt + EMMC_STATUS, SR_READ_TRANSFER);
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ret = raspi_transfer_command(pdat, cmd);
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if (ret < 0) return ret;
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ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
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}
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else if(dat->flag & DATA_DIR_WRITE)
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{
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ret = raspi_transfer_command(pdat, cmd);
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if (ret < 0) return ret;
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write32(pdat->virt + EMMC_STATUS, SR_WRITE_TRANSFER);
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ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
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}
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return ret;
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}
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static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data;
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struct sdhci_cmd_t cmd;
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struct sdhci_cmd_t stop;
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struct sdhci_data_t dat;
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rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t));
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rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t));
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rt_memset(&dat, 0, sizeof(struct sdhci_data_t));
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cmd.cmdidx = req->cmd->cmd_code;
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EMMCCommand* cmdtab = &sdCommandTable[cmd.cmdidx];
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cmd.cmdarg = req->cmd->arg;
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cmd.resptype = cmdtab->resp;
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if(req->data)
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{
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dat.buf = (rt_uint8_t *)req->data->buf;
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dat.flag = req->data->flags;
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dat.blksz = req->data->blksize;
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dat.blkcnt = req->data->blks;
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req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat);
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}
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else
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{
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req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL);
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}
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req->cmd->resp[3] = cmd.response[3];
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req->cmd->resp[2] = cmd.response[2];
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req->cmd->resp[1] = cmd.response[1];
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req->cmd->resp[0] = cmd.response[0];
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if (req->stop)
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{
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stop.cmdidx = req->stop->cmd_code;
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cmdtab = &sdCommandTable[cmd.cmdidx];
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stop.cmdarg = req->stop->arg;
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cmd.resptype = cmdtab->resp;
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req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL);
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}
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mmcsd_req_complete(host);
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}
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static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
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{
|
||
|
|
struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
|
||
|
|
|
||
|
|
if(!dat)
|
||
|
|
return raspi_transfer_command(pdat, cmd);
|
||
|
|
|
||
|
|
return raspi_transfer_data(pdat, cmd, dat);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
//#ifdef CONFIG_MMC_USE_DMA
|
||
|
|
//#ifdef BSP_USING_SDIO0
|
||
|
|
////ALIGN(32) static rt_uint8_t dma_buffer[64 * 1024];
|
||
|
|
//static rt_uint8_t dma_buffer[64 * 1024];
|
||
|
|
//#endif
|
||
|
|
//#endif
|
||
|
|
|
||
|
|
|
||
|
|
static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
|
||
|
|
{
|
||
|
|
struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data;
|
||
|
|
sdhci_setclock(sdhci, io_cfg->clock);
|
||
|
|
sdhci_setwidth(sdhci, io_cfg->bus_width);
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_int32_t mmc_card_status(struct rt_mmcsd_host *host)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mmc_enable_irq(struct rt_mmcsd_host *host, rt_int32_t en)
|
||
|
|
{
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t sdhci_detect(struct sdhci_t * sdhci)
|
||
|
|
{
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width)
|
||
|
|
{
|
||
|
|
rt_uint32_t temp = 0;
|
||
|
|
struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
|
||
|
|
temp = read32((pdat->virt + EMMC_CONTROL0));
|
||
|
|
temp |= C0_HCTL_HS_EN;
|
||
|
|
temp |= C0_HCTL_DWITDH; // always use 4 data lines:
|
||
|
|
write32((pdat->virt + EMMC_CONTROL0), temp);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_uint32_t sdhci_getdivider( rt_uint32_t sdHostVer, rt_uint32_t freq )
|
||
|
|
{
|
||
|
|
rt_uint32_t divisor;
|
||
|
|
rt_uint32_t closest = 41666666 / freq;
|
||
|
|
rt_uint32_t shiftcount = __rt_fls(closest - 1);
|
||
|
|
|
||
|
|
|
||
|
|
if (shiftcount > 0) shiftcount--;
|
||
|
|
if (shiftcount > 7) shiftcount = 7;
|
||
|
|
if (sdHostVer > HOST_SPEC_V2)
|
||
|
|
divisor = closest;
|
||
|
|
else
|
||
|
|
divisor = (1 << shiftcount);
|
||
|
|
|
||
|
|
if (divisor <= 2) {
|
||
|
|
divisor = 2;
|
||
|
|
shiftcount = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_uint32_t hi = 0;
|
||
|
|
if (sdHostVer > HOST_SPEC_V2)
|
||
|
|
hi = (divisor & 0x300) >> 2;
|
||
|
|
rt_uint32_t lo = (divisor & 0x0ff);
|
||
|
|
rt_uint32_t cdiv = (lo << 8) + hi;
|
||
|
|
return cdiv;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
|
||
|
|
{
|
||
|
|
rt_uint32_t temp = 0;
|
||
|
|
rt_uint32_t sdHostVer = 0;
|
||
|
|
int count = 100000;
|
||
|
|
struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
|
||
|
|
|
||
|
|
temp = read32(pdat->virt + EMMC_STATUS);
|
||
|
|
while((temp & (SR_CMD_INHIBIT | SR_DAT_INHIBIT))&&(--count))
|
||
|
|
bcm283x_clo_delayMicros(1);
|
||
|
|
|
||
|
|
if( count <= 0 )
|
||
|
|
{
|
||
|
|
rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n", temp);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Switch clock off.
|
||
|
|
temp = read32((pdat->virt + EMMC_CONTROL1));
|
||
|
|
temp |= ~C1_CLK_EN;
|
||
|
|
write32((pdat->virt + EMMC_CONTROL1),temp);
|
||
|
|
|
||
|
|
bcm283x_clo_delayMicros(10);
|
||
|
|
|
||
|
|
// Request the new clock setting and enable the clock
|
||
|
|
temp = read32(pdat->virt + EMMC_SLOTISR_VER);
|
||
|
|
sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT;
|
||
|
|
|
||
|
|
int cdiv = sdhci_getdivider(sdHostVer, clock);
|
||
|
|
temp = read32((pdat->virt + EMMC_CONTROL1));
|
||
|
|
temp = (temp & 0xffff003f) | cdiv;
|
||
|
|
write32((pdat->virt + EMMC_CONTROL1),temp);
|
||
|
|
bcm283x_clo_delayMicros(10);
|
||
|
|
|
||
|
|
// Enable the clock.
|
||
|
|
temp = read32(pdat->virt + EMMC_CONTROL1);
|
||
|
|
temp |= C1_CLK_EN;
|
||
|
|
write32((pdat->virt + EMMC_CONTROL1),temp);
|
||
|
|
bcm283x_clo_delayMicros(10);
|
||
|
|
|
||
|
|
// Wait for clock to be stable.
|
||
|
|
count = 10000;
|
||
|
|
temp = read32(pdat->virt + EMMC_CONTROL1);
|
||
|
|
while( !(temp & C1_CLK_STABLE) && count-- )
|
||
|
|
bcm283x_clo_delayMicros(10);
|
||
|
|
|
||
|
|
if( count <= 0 )
|
||
|
|
{
|
||
|
|
rt_kprintf("EMMC: ERROR: failed to get stable clock.\n");
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_mmcsd_host_ops ops =
|
||
|
|
{
|
||
|
|
mmc_request_send,
|
||
|
|
mmc_set_iocfg,
|
||
|
|
RT_NULL,
|
||
|
|
RT_NULL,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void sdmmc_gpio_init()
|
||
|
|
{
|
||
|
|
int pin;
|
||
|
|
|
||
|
|
for (pin = BCM_GPIO_PIN_48; pin <= BCM_GPIO_PIN_53; pin++)
|
||
|
|
{
|
||
|
|
bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
|
||
|
|
bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_ALT3);
|
||
|
|
}
|
||
|
|
bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
|
||
|
|
bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
|
||
|
|
}
|
||
|
|
|
||
|
|
int raspi_sdmmc_init(void)
|
||
|
|
{
|
||
|
|
rt_uint32_t virt;
|
||
|
|
rt_uint32_t id;
|
||
|
|
struct rt_mmcsd_host * host = RT_NULL;
|
||
|
|
struct sdhci_pdata_t * pdat = RT_NULL;
|
||
|
|
struct sdhci_t * sdhci = RT_NULL;
|
||
|
|
|
||
|
|
rt_kprintf("raspi_sdmmc_init start\n");
|
||
|
|
|
||
|
|
#ifdef BSP_USING_SDIO0
|
||
|
|
host = mmcsd_alloc_host();
|
||
|
|
if (!host)
|
||
|
|
{
|
||
|
|
rt_kprintf("alloc host failed");
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
|
||
|
|
sdhci = rt_malloc(sizeof(struct sdhci_t));
|
||
|
|
if (!sdhci)
|
||
|
|
{
|
||
|
|
rt_kprintf("alloc sdhci failed");
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
rt_memset(sdhci, 0, sizeof(struct sdhci_t));
|
||
|
|
|
||
|
|
rt_kprintf(">> sdmmc_gpio_init\n");
|
||
|
|
sdmmc_gpio_init();
|
||
|
|
rt_kprintf("<< sdmmc_gpio_init\n");
|
||
|
|
|
||
|
|
virt = MMC0_BASE_ADDR;
|
||
|
|
|
||
|
|
pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
|
||
|
|
RT_ASSERT(pdat != RT_NULL);
|
||
|
|
|
||
|
|
pdat->virt = (rt_uint32_t)virt;
|
||
|
|
|
||
|
|
sdhci->name = "sd0";
|
||
|
|
sdhci->voltages = VDD_33_34;
|
||
|
|
sdhci->width = MMCSD_BUSWIDTH_4;
|
||
|
|
sdhci->clock = 26 * 1000 * 1000;
|
||
|
|
sdhci->removeable = RT_TRUE;
|
||
|
|
|
||
|
|
sdhci->detect = sdhci_detect;
|
||
|
|
sdhci->setwidth = sdhci_setwidth;
|
||
|
|
sdhci->setclock = sdhci_setclock;
|
||
|
|
sdhci->transfer = sdhci_transfer;
|
||
|
|
sdhci->priv = pdat;
|
||
|
|
//write32(pdat->virt + PL180_POWER, 0xbf);
|
||
|
|
|
||
|
|
host->ops = &ops;
|
||
|
|
host->freq_min = 400000;
|
||
|
|
host->freq_max = 50000000;
|
||
|
|
host->valid_ocr = VDD_32_33 | VDD_33_34;
|
||
|
|
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
|
||
|
|
host->max_seg_size = 2048;
|
||
|
|
host->max_dma_segs = 10;
|
||
|
|
host->max_blk_size = 512;
|
||
|
|
host->max_blk_count = 4096;
|
||
|
|
|
||
|
|
host->private_data = sdhci;
|
||
|
|
|
||
|
|
mmcsd_change(host);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
|
||
|
|
err:
|
||
|
|
if(host) rt_free(host);
|
||
|
|
if(sdhci) rt_free(sdhci);
|
||
|
|
|
||
|
|
return -RT_EIO;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
INIT_APP_EXPORT(raspi_sdmmc_init);
|
||
|
|
#endif
|