874 lines
36 KiB
C
874 lines
36 KiB
C
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/*!
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*******************************************************************************
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**
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** \file gh_dma.h
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**
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** \brief DMA Engine Subsystem.
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**
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** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \note Do not modify this file as it is generated automatically.
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**
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******************************************************************************/
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#ifndef _GH_DMA_H
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#define _GH_DMA_H
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#ifdef __LINUX__
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#include "reg4linux.h"
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#else
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#define FIO_ADDRESS(block,address) (address)
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#define FIO_MOFFSET(block,moffset) (moffset)
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#endif
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#ifndef __LINUX__
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#include "gtypes.h" /* global type definitions */
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#include "gh_lib_cfg.h" /* configuration */
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#endif
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#define GH_DMA_ENABLE_DEBUG_PRINT 0
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#ifdef __LINUX__
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#define GH_DMA_DEBUG_PRINT_FUNCTION printk
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#else
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#define GH_DMA_DEBUG_PRINT_FUNCTION printf
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#endif
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#ifndef __LINUX__
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#if GH_DMA_ENABLE_DEBUG_PRINT
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#include <stdio.h>
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#endif
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#endif
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/* check configuration */
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#ifndef GH_INLINE_LEVEL
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#error "GH_INLINE_LEVEL is not defined!"
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#endif
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#if GH_INLINE_LEVEL > 2
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#error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
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#endif
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#ifndef GH_INLINE
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#error "GH_INLINE is not defined!"
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#endif
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/* disable inlining for debugging */
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#ifdef DEBUG
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#undef GH_INLINE_LEVEL
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#define GH_INLINE_LEVEL 0
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#endif
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/*----------------------------------------------------------------------------*/
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/* registers */
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/*----------------------------------------------------------------------------*/
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#define REG_DMA_CONTROL FIO_ADDRESS(DMA,0x9000331C) /* read/write */
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#define REG_DMA_SOURCE_ADDRESS FIO_ADDRESS(DMA,0x90003320) /* read/write */
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#define REG_DMA_DESTINATION_ADDRESS FIO_ADDRESS(DMA,0x90003324) /* read/write */
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#define REG_DMA_STATUS FIO_ADDRESS(DMA,0x90003328) /* read/write */
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#define REG_DMA_DESCRIPTOR_ADDRESS FIO_ADDRESS(DMA,0x90003308) /* read/write */
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#define REG_DMA_IR FIO_ADDRESS(DMA,0x90003304) /* read */
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/*----------------------------------------------------------------------------*/
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/* bit group structures */
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/*----------------------------------------------------------------------------*/
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typedef union { /* DMA_Control */
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U32 all;
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struct {
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U32 count : 22;
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U32 ts : 2;
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U32 blk : 3;
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U32 ni : 1;
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U32 rm : 1;
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U32 wm : 1;
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U32 d : 1;
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U32 en : 1;
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} bitc;
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} GH_DMA_CONTROL_S;
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typedef union { /* DMA_Status */
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U32 all;
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struct {
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U32 count : 22;
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U32 dn : 1;
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U32 ae : 1;
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U32 rwe : 1;
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U32 be : 1;
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U32 me : 1;
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U32 od : 1;
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U32 dd : 1;
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U32 da : 1;
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U32 oe : 1;
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U32 dm : 1;
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} bitc;
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} GH_DMA_STATUS_S;
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typedef union { /* DMA_IR */
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U32 all;
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struct {
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U32 i0 : 1;
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U32 i1 : 1;
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U32 i2 : 1;
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U32 i3 : 1;
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U32 : 28;
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} bitc;
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} GH_DMA_IR_S;
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/*----------------------------------------------------------------------------*/
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/* mirror variables */
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/*----------------------------------------------------------------------------*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* register DMA_Control (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'DMA_Control'. */
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void GH_DMA_set_Control(U8 index, U32 data);
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/*! \brief Reads the register 'DMA_Control'. */
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U32 GH_DMA_get_Control(U8 index);
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/*! \brief Writes the bit group 'count' of register 'DMA_Control'. */
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void GH_DMA_set_Control_count(U8 index, U32 data);
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/*! \brief Reads the bit group 'count' of register 'DMA_Control'. */
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U32 GH_DMA_get_Control_count(U8 index);
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/*! \brief Writes the bit group 'ts' of register 'DMA_Control'. */
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void GH_DMA_set_Control_ts(U8 index, U8 data);
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/*! \brief Reads the bit group 'ts' of register 'DMA_Control'. */
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U8 GH_DMA_get_Control_ts(U8 index);
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/*! \brief Writes the bit group 'blk' of register 'DMA_Control'. */
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void GH_DMA_set_Control_blk(U8 index, U8 data);
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/*! \brief Reads the bit group 'blk' of register 'DMA_Control'. */
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U8 GH_DMA_get_Control_blk(U8 index);
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/*! \brief Writes the bit group 'ni' of register 'DMA_Control'. */
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void GH_DMA_set_Control_ni(U8 index, U8 data);
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/*! \brief Reads the bit group 'ni' of register 'DMA_Control'. */
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U8 GH_DMA_get_Control_ni(U8 index);
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/*! \brief Writes the bit group 'rm' of register 'DMA_Control'. */
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void GH_DMA_set_Control_rm(U8 index, U8 data);
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/*! \brief Reads the bit group 'rm' of register 'DMA_Control'. */
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U8 GH_DMA_get_Control_rm(U8 index);
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/*! \brief Writes the bit group 'wm' of register 'DMA_Control'. */
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void GH_DMA_set_Control_wm(U8 index, U8 data);
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/*! \brief Reads the bit group 'wm' of register 'DMA_Control'. */
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U8 GH_DMA_get_Control_wm(U8 index);
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/*! \brief Writes the bit group 'd' of register 'DMA_Control'. */
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void GH_DMA_set_Control_d(U8 index, U8 data);
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/*! \brief Reads the bit group 'd' of register 'DMA_Control'. */
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U8 GH_DMA_get_Control_d(U8 index);
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/*! \brief Writes the bit group 'en' of register 'DMA_Control'. */
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void GH_DMA_set_Control_en(U8 index, U8 data);
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/*! \brief Reads the bit group 'en' of register 'DMA_Control'. */
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U8 GH_DMA_get_Control_en(U8 index);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_DMA_set_Control(U8 index, U32 data)
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{
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*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = data;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control] <-- 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),data,data);
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#endif
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}
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GH_INLINE U32 GH_DMA_get_Control(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control] --> 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
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#endif
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return value;
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}
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GH_INLINE void GH_DMA_set_Control_count(U8 index, U32 data)
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{
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GH_DMA_CONTROL_S d;
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d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
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d.bitc.count = data;
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*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_count] <-- 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
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#endif
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}
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GH_INLINE U32 GH_DMA_get_Control_count(U8 index)
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{
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GH_DMA_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
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tmp_value.all = value;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_count] --> 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
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#endif
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return tmp_value.bitc.count;
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}
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GH_INLINE void GH_DMA_set_Control_ts(U8 index, U8 data)
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{
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GH_DMA_CONTROL_S d;
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d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
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d.bitc.ts = data;
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*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_ts] <-- 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_DMA_get_Control_ts(U8 index)
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{
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GH_DMA_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
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tmp_value.all = value;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_ts] --> 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
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#endif
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return tmp_value.bitc.ts;
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}
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GH_INLINE void GH_DMA_set_Control_blk(U8 index, U8 data)
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{
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GH_DMA_CONTROL_S d;
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d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
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d.bitc.blk = data;
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*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_blk] <-- 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_DMA_get_Control_blk(U8 index)
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{
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GH_DMA_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
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tmp_value.all = value;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_blk] --> 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
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#endif
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return tmp_value.bitc.blk;
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}
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GH_INLINE void GH_DMA_set_Control_ni(U8 index, U8 data)
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{
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GH_DMA_CONTROL_S d;
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d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
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d.bitc.ni = data;
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*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_ni] <-- 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_DMA_get_Control_ni(U8 index)
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{
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GH_DMA_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
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tmp_value.all = value;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_ni] --> 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
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#endif
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return tmp_value.bitc.ni;
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}
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GH_INLINE void GH_DMA_set_Control_rm(U8 index, U8 data)
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{
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GH_DMA_CONTROL_S d;
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d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
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d.bitc.rm = data;
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*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_rm] <-- 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_DMA_get_Control_rm(U8 index)
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{
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GH_DMA_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
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tmp_value.all = value;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_rm] --> 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
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#endif
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return tmp_value.bitc.rm;
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}
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GH_INLINE void GH_DMA_set_Control_wm(U8 index, U8 data)
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{
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GH_DMA_CONTROL_S d;
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d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
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d.bitc.wm = data;
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*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
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#if GH_DMA_ENABLE_DEBUG_PRINT
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GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_wm] <-- 0x%08x\n",
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(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_DMA_get_Control_wm(U8 index)
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{
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GH_DMA_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_wm] --> 0x%08x\n",
|
||
|
|
(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.wm;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Control_d(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_CONTROL_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.d = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_d] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Control_d(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_CONTROL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_d] --> 0x%08x\n",
|
||
|
|
(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.d;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Control_en(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_CONTROL_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.en = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Control_en] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Control_en(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_CONTROL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Control_en] --> 0x%08x\n",
|
||
|
|
(REG_DMA_CONTROL + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.en;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* register DMA_Source_Address (read/write) */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
#if GH_INLINE_LEVEL == 0
|
||
|
|
/*! \brief Writes the register 'DMA_Source_Address'. */
|
||
|
|
void GH_DMA_set_Source_Address(U8 index, U32 data);
|
||
|
|
/*! \brief Reads the register 'DMA_Source_Address'. */
|
||
|
|
U32 GH_DMA_get_Source_Address(U8 index);
|
||
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
||
|
|
GH_INLINE void GH_DMA_set_Source_Address(U8 index, U32 data)
|
||
|
|
{
|
||
|
|
*(volatile U32 *)(REG_DMA_SOURCE_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)) = data;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Source_Address] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_SOURCE_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)),data,data);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U32 GH_DMA_get_Source_Address(U8 index)
|
||
|
|
{
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_SOURCE_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Source_Address] --> 0x%08x\n",
|
||
|
|
(REG_DMA_SOURCE_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* register DMA_Destination_Address (read/write) */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
#if GH_INLINE_LEVEL == 0
|
||
|
|
/*! \brief Writes the register 'DMA_Destination_Address'. */
|
||
|
|
void GH_DMA_set_Destination_Address(U8 index, U32 data);
|
||
|
|
/*! \brief Reads the register 'DMA_Destination_Address'. */
|
||
|
|
U32 GH_DMA_get_Destination_Address(U8 index);
|
||
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
||
|
|
GH_INLINE void GH_DMA_set_Destination_Address(U8 index, U32 data)
|
||
|
|
{
|
||
|
|
*(volatile U32 *)(REG_DMA_DESTINATION_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)) = data;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Destination_Address] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_DESTINATION_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)),data,data);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U32 GH_DMA_get_Destination_Address(U8 index)
|
||
|
|
{
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_DESTINATION_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Destination_Address] --> 0x%08x\n",
|
||
|
|
(REG_DMA_DESTINATION_ADDRESS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* register DMA_Status (read/write) */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
#if GH_INLINE_LEVEL == 0
|
||
|
|
/*! \brief Writes the register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status(U8 index, U32 data);
|
||
|
|
/*! \brief Reads the register 'DMA_Status'. */
|
||
|
|
U32 GH_DMA_get_Status(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'count' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_count(U8 index, U32 data);
|
||
|
|
/*! \brief Reads the bit group 'count' of register 'DMA_Status'. */
|
||
|
|
U32 GH_DMA_get_Status_count(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'dn' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_dn(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'dn' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_dn(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'ae' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_ae(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'ae' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_ae(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'rwe' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_rwe(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'rwe' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_rwe(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'be' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_be(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'be' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_be(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'me' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_me(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'me' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_me(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'od' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_od(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'od' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_od(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'dd' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_dd(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'dd' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_dd(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'da' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_da(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'da' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_da(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'oe' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_oe(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'oe' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_oe(U8 index);
|
||
|
|
/*! \brief Writes the bit group 'dm' of register 'DMA_Status'. */
|
||
|
|
void GH_DMA_set_Status_dm(U8 index, U8 data);
|
||
|
|
/*! \brief Reads the bit group 'dm' of register 'DMA_Status'. */
|
||
|
|
U8 GH_DMA_get_Status_dm(U8 index);
|
||
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
||
|
|
GH_INLINE void GH_DMA_set_Status(U8 index, U32 data)
|
||
|
|
{
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = data;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),data,data);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U32 GH_DMA_get_Status(U8 index)
|
||
|
|
{
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_count(U8 index, U32 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.count = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_count] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U32 GH_DMA_get_Status_count(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_count] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.count;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_dn(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.dn = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_dn] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_dn(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_dn] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.dn;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_ae(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.ae = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_ae] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_ae(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_ae] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.ae;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_rwe(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.rwe = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_rwe] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_rwe(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_rwe] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.rwe;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_be(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.be = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_be] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_be(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_be] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.be;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_me(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.me = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_me] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_me(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_me] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.me;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_od(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.od = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_od] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_od(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_od] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.od;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_dd(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.dd = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_dd] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_dd(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_dd] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.dd;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_da(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.da = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_da] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_da(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_da] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.da;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_oe(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.oe = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_oe] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_oe(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_oe] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.oe;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_DMA_set_Status_dm(U8 index, U8 data)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S d;
|
||
|
|
d.all = *(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010));
|
||
|
|
d.bitc.dm = data;
|
||
|
|
*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)) = d.all;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Status_dm] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_Status_dm(U8 index)
|
||
|
|
{
|
||
|
|
GH_DMA_STATUS_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)));
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Status_dm] --> 0x%08x\n",
|
||
|
|
(REG_DMA_STATUS + index * FIO_MOFFSET(DMA,0x00000010)),value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.dm;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* register DMA_Descriptor_Address (read/write) */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
#if GH_INLINE_LEVEL == 0
|
||
|
|
/*! \brief Writes the register 'DMA_Descriptor_Address'. */
|
||
|
|
void GH_DMA_set_Descriptor_Address(U8 index, U32 data);
|
||
|
|
/*! \brief Reads the register 'DMA_Descriptor_Address'. */
|
||
|
|
U32 GH_DMA_get_Descriptor_Address(U8 index);
|
||
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
||
|
|
GH_INLINE void GH_DMA_set_Descriptor_Address(U8 index, U32 data)
|
||
|
|
{
|
||
|
|
*(volatile U32 *)(REG_DMA_DESCRIPTOR_ADDRESS + index * FIO_MOFFSET(DMA,0x00000004)) = data;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_DMA_set_Descriptor_Address] <-- 0x%08x\n",
|
||
|
|
(REG_DMA_DESCRIPTOR_ADDRESS + index * FIO_MOFFSET(DMA,0x00000004)),data,data);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U32 GH_DMA_get_Descriptor_Address(U8 index)
|
||
|
|
{
|
||
|
|
U32 value = (*(volatile U32 *)(REG_DMA_DESCRIPTOR_ADDRESS + index * FIO_MOFFSET(DMA,0x00000004)));
|
||
|
|
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_Descriptor_Address] --> 0x%08x\n",
|
||
|
|
(REG_DMA_DESCRIPTOR_ADDRESS + index * FIO_MOFFSET(DMA,0x00000004)),value);
|
||
|
|
#endif
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* register DMA_IR (read) */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
#if GH_INLINE_LEVEL == 0
|
||
|
|
/*! \brief Reads the register 'DMA_IR'. */
|
||
|
|
U32 GH_DMA_get_IR(void);
|
||
|
|
/*! \brief Reads the bit group 'i0' of register 'DMA_IR'. */
|
||
|
|
U8 GH_DMA_get_IR_i0(void);
|
||
|
|
/*! \brief Reads the bit group 'i1' of register 'DMA_IR'. */
|
||
|
|
U8 GH_DMA_get_IR_i1(void);
|
||
|
|
/*! \brief Reads the bit group 'i2' of register 'DMA_IR'. */
|
||
|
|
U8 GH_DMA_get_IR_i2(void);
|
||
|
|
/*! \brief Reads the bit group 'i3' of register 'DMA_IR'. */
|
||
|
|
U8 GH_DMA_get_IR_i3(void);
|
||
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
||
|
|
GH_INLINE U32 GH_DMA_get_IR(void)
|
||
|
|
{
|
||
|
|
U32 value = (*(volatile U32 *)REG_DMA_IR);
|
||
|
|
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_IR] --> 0x%08x\n",
|
||
|
|
REG_DMA_IR,value);
|
||
|
|
#endif
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_IR_i0(void)
|
||
|
|
{
|
||
|
|
GH_DMA_IR_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_DMA_IR);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_IR_i0] --> 0x%08x\n",
|
||
|
|
REG_DMA_IR,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.i0;
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_IR_i1(void)
|
||
|
|
{
|
||
|
|
GH_DMA_IR_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_DMA_IR);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_IR_i1] --> 0x%08x\n",
|
||
|
|
REG_DMA_IR,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.i1;
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_IR_i2(void)
|
||
|
|
{
|
||
|
|
GH_DMA_IR_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_DMA_IR);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_IR_i2] --> 0x%08x\n",
|
||
|
|
REG_DMA_IR,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.i2;
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_DMA_get_IR_i3(void)
|
||
|
|
{
|
||
|
|
GH_DMA_IR_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_DMA_IR);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_DMA_ENABLE_DEBUG_PRINT
|
||
|
|
GH_DMA_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_DMA_get_IR_i3] --> 0x%08x\n",
|
||
|
|
REG_DMA_IR,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.i3;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* init function */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/*! \brief Initialises the registers and mirror variables. */
|
||
|
|
void GH_DMA_init(void);
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _GH_DMA_H */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* end of file */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
|