251 lines
10 KiB
C
251 lines
10 KiB
C
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/*!
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*******************************************************************************
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**
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** \file gd_int.h
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**
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** \brief INT (interrupt) driver
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**
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** This driver provides functions and structures required to
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** access the GK6202 interrupt engine.
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**
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** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \version
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**
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******************************************************************************/
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#ifndef GD_INT_H
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#define GD_INT_H
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#include <gtypes.h>
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#include <gmodids.h>
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#define GD_VIC_INSTANCES 2
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#define GD_INT_VEC_OFFSET 32
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/*---------------------------------------------------------------------------*/
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/* constants and macros */
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/*---------------------------------------------------------------------------*/
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#define GD_INT_ERR_BASE (GD_INT_MODULE_ID<<16) //!< The INT base error code.
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/*!
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*******************************************************************************
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**
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** \anchor int_defines
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** \name interrupt driver specific macros
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**
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** This section defines various macros required to control interrupts.
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**
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******************************************************************************/
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/*@{*/
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#define GD_INT_NO_INVERT_IRQ 0 //!< The IRQ signal is not inverted.
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#define GD_INT_INVERT_IRQ 1 //!< The IRQ signal is inverted.
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#define GD_INT_LOW_PRIORITY 0 //!< Fast Interrupt Request (FIQ) for fast, low latency interrupt handling
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#define GD_INT_MID_PRIORITY 1 //!< Interrupt Request (IRQ) for more general interrupts
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#define GD_INT_DISABLED 0 //!< Interrupts are disabled.
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#define GD_INT_ENABLED 1 //!< Interrupts are enabled.
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/*@}*/
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#define GD_INT_RISING_EDGE 0
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#define GD_INT_FALLING_EDGE 1
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#define GD_INT_BOTH_EDGES 2
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#define GD_INT_LEVEL_LOW 3
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#define GD_INT_LEVEL_HIGH 4
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/*!
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*******************************************************************************
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**
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** \brief Interrupt vectors
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**
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** The list below describes all available interrupt sources,
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** a table containing the real interrupt service routines can
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** be stored in the ARC aux. register 0x0203.
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**
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** The first three interrupt vectors are non-maskable, their
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** priorty is high.
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** All other interrupts are maskable and the priority can be set
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** either to medium (1) or low (2).
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**
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******************************************************************************/
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enum
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{
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GD_INT_RESERVED1_00_IRQ = 0, //!<
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GD_INT_ETH_IRQ = 1, //!< level, Ethernet 1
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GD_INT_IDSP_ERROR_IRQ = 2, //!< edge, iDSP error
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GD_INT_XIU_TIMEOUT_IRQ = 3, //!< edge
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GD_INT_RESERVED1_04_IRQ = 4, //!<
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GD_INT_RESERVED1_05_IRQ = 5, //!<
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GD_INT_RESERVED1_06_IRQ = 6, //!<
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GD_INT_CODING_ORC_VOUT1_IRQ =7, //!< edge, Coding Orc VOUT1
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GD_INT_SD_CONTROLLER_IRQ = 8, //!< level, SD controller
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GD_INT_IDC_IRQ = 9, //!< level, i2c read/write, I2C0
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GD_INT_SSI_SPI_IRQ = 10, //!< level, Synchronous Serial Interface (SSI, SPI)
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GD_INT_WDT_IRQ = 11, //!< edge, Watchdog (WDT)
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GD_INT_RESERVED1_12_IRQ = 12, //!<
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GD_INT_SD2_CARD_DETECT_IRQ = 13, //!<
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GD_INT_SD_CARD_DETECT_IRQ = 14, //!< Both edges, SD card detect (state of SMIO5 pin)
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GD_INT_UART1_IRQ = 15, //!< level, uart read/write, UART1
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GD_INT_GPIO0_IRQ = 16, //!< level, GPIO0
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GD_INT_RESERVED1_17_IRQ = 17, //!< level, UART2
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GD_INT_TIMER1_IRQ = 18, //!< edge, timer#1
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GD_INT_TIMER2_IRQ = 19, //!< edge, timer#2
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GD_INT_TIMER3_IRQ = 20, //!< edge, timer#3
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GD_INT_DMA_IRQ = 21, //!< level, DMA
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GD_INT_SD2_CONTROLLER_IRQ = 22, //!< level, SD2 controller
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GD_INT_RESERVED1_23_IRQ = 23, //!<
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GD_INT_CODING_ORC_VIN_IRQ = 24, //!< edge, Coding Orc VIN
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GD_INT_CORDING_ORC_VDSP_IRQ = 25, //!< edge, Cording Orc vDSP
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GD_INT_USB_IRQ = 26, //!< level, USB
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GD_INT_UART2_IRQ = 27, //!<
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GD_INT_RESERVED1_28_IRQ = 28, //!<
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GD_INT_AUDIO_I2S_TX_IRQ = 29, //!< level, Audio (I2S) TX
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GD_INT_AUDIO_I2S_RX_IRQ = 30, //!< level, Audio (I2S) RX
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GD_INT_UART_IRQ = 31, //!< level, UART0
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#if (GD_VIC_INSTANCES >= 2)
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GD_INT_RESERVED2_00_IRQ = ( 0 + 32), //!<
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GD_INT_RESERVED2_01_IRQ = ( 1 + 32), //!<
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GD_INT_RESERVED2_02_IRQ = ( 2 + 32), //!<
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GD_INT_RESERVED2_03_IRQ = ( 3 + 32), //!<
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GD_INT_RESERVED2_04_IRQ = ( 4 + 32), //!<
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GD_INT_RESERVED2_05_IRQ = ( 5 + 32), //!<
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GD_INT_RESERVED2_06_IRQ = ( 6 + 32), //!<
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GD_INT_RESERVED2_07_IRQ = ( 7 + 32), //!<
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GD_INT_AUDIO_PHY_TX_IRQ = ( 8 + 32), //!<level, Audio PHY TX INT
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GD_INT_AUDIO_PHY_RX_IRQ = ( 9 + 32), //!<level, Audio PHY RX INT
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GD_INT_RESERVED2_10_IRQ = (10 + 32), //!<
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GD_INT_RESERVED2_11_IRQ = (11 + 32), //!<
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GD_INT_RESERVED2_12_IRQ = (12 + 32), //!<
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GD_INT_RESERVED2_13_IRQ = (13 + 32), //!<
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GD_INT_RESERVED2_14_IRQ = (14 + 32), //!<
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GD_INT_RESERVED2_15_IRQ = (15 + 32), //!<
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GD_INT_RESERVED2_16_IRQ = (16 + 32), //!<
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GD_INT_RESERVED2_17_IRQ = (17 + 32), //!<*/
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GD_INT_CODING_ORC_VOUT0_IRQ=(18 + 32), //!< edge, Coding Orc VOUT0
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GD_INT_CRYPTO_OUTPUT_READY_IRQ=(19 + 32), //!< edge, AES/DES output ready from Crypt block--AES/DES finished
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GD_INT_PERFORMANCE_MONITOR_IRQ=(20 + 32), //!<
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GD_INT_RESERVED2_21_IRQ = (21 + 32), //!<
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GD_INT_GDMA_COMPLETION_IRQ = (22 + 32), //!<edge, GDMA Completion
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GD_INT_RESERVED2_23_IRQ = (23 + 32), //!<
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GD_INT_ADC_LEVEL_CHANGE_IRQ=(24 + 32), //!< level, ADC level change
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GD_INT_RESERVED2_25_IRQ = (25 + 32), //!<
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GD_INT_IDC2_IRQ = (26 + 32), //!< level, IDC2
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GD_INT_IDSP_LAST_PIXEL_IRQ= (27 + 32), //!< edge, iDSP last pixel
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GD_INT_IDSP_VSYNC_IRQ = (28 + 32), //!< edge, iDSP Vsync (VIN on master mode)
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GD_INT_IDSP_SENSOR_VSYNC_IRQ=(29+ 32), //!< edge, iDSP sensor Vsync (VIN on slave mode)
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GD_INT_PMU_IRQ = (30 + 32), //!< level, PMU
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GD_INT_SSI2_IRQ = (31 + 32), //!< level, SSI2
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#endif
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};
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// modify for rtos
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#define GD_INT_LAST_IRQ (31 + 32)
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/*---------------------------------------------------------------------------*/
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/* types, enums and structures */
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/*---------------------------------------------------------------------------*/
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/*!
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*******************************************************************************
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**
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** \brief Interrupt initialization parameter structure.
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**
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** \sa GD_INT_Init()
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**
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******************************************************************************/
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typedef struct
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{
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void (*resetFct)(void); //!< The reset handler.
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void (*memExceptionFct)(void); //!< The memory exception handler.
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void (*instructErrorFct)(void); //!< The Instruction Error handler.
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} GD_INT_INIT_PARAMS_S;
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/*!
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*******************************************************************************
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**
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** \brief Interrupt driver open parameter structure.
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**
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** \sa GD_INT_Open()
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**
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******************************************************************************/
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typedef struct
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{
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S8 type; //!< the interrupt vector to access
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S8 active; //!< activation, either GD_INT_INVERT_IRQ or GD_INT_NO_INVERT_IRQ
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S8 sensitivity; //!< sensitivity, GD_INT_RISING_EDGE or GD_INT_FALLING_EDGE
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//!< or GD_INT_BOTH_EDGES or GD_INT_LEVEL_LOW or GD_INT_LEVEL_HIGH
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S8 priority; //!< priority, either GD_INT_MID_PRIORITY or GD_INT_LOW_PRIORITY
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union
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{
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GISR1 (*lowPrio)(void);
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GISR2 (*midPrio)(void);
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}isrFct; //!< the interrupt service function
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} GD_INT_OPEN_PARAMS_S;
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/*!
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*******************************************************************************
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**
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** \brief Interrupt processor function type.
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**
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******************************************************************************/
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/*! Pointer to the interrupt handler function of the driver. */
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typedef GISR1(*GD_ARM_INTR_IsrFuncT)(void);
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/*! //!< Pointer to the processing function of the driver. */
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typedef void(*GD_INT_PROCESSOR_F)(void* data);
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/*!
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*******************************************************************************
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**
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** \brief Interrupt driver data structure
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**
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******************************************************************************/
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typedef struct
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{
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U32 length; //!< The length of the driver data in bytes.
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void* data; //!< Pointer to driver specific data structure.
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GD_INT_PROCESSOR_F processor; //!< Pointer to interrupt processing function.
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} GD_INT_DATA_S;
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/*!
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*******************************************************************************
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**
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** \brief Interrupt handler function type
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**
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******************************************************************************/
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/*! Pointer to the interrupt handler function of the driver. */
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typedef GD_INT_DATA_S*(*GD_INT_HANDLER_F)(void);
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/*---------------------------------------------------------------------------*/
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/* function prototypes */
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/*---------------------------------------------------------------------------*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void GD_INT_Close(GD_HANDLE *handleP);
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GERR GD_INT_Init(GD_INT_INIT_PARAMS_S *initParams);
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GERR GD_INT_Open(GD_INT_OPEN_PARAMS_S *openParams, GD_HANDLE *handle);
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void GD_INT_GetIrqSettings(S8 type, S8 *prio, S8 *act, S8 *sens, S8 *mask);
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U32 GD_INT_GetUsedIrqs(void);
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void GD_INT_SetInterruptTrigger(S8 vec);
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void GD_INT_SetVector(S8 vector, void (*target)());
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void GD_INT_SetHandler(S8 vector, GD_INT_HANDLER_F handler);
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GD_INT_HANDLER_F GD_INT_GetHandler(S8 vector);
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void GD_INT_InvalidateDataCache(void);
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void GD_INT_InvalidateInstructionCache(void);
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void GD_INT_Enable(GD_HANDLE *handleP,U8 enable);
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void GD_INT_DisableAllInterrupts(void);
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void GD_INT_EnableAllInterrupts(void);
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void GD_IRQ_ISR(void);
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void GD_FIQ_ISR(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/* end of gd_int.h */
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