2018-11-29 17:00:22 +08:00
|
|
|
/*
|
2021-03-08 22:40:39 +08:00
|
|
|
* Copyright (c) 2006-2021, RT-Thread Development Team
|
2018-11-29 17:00:22 +08:00
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*
|
|
|
|
* Change Logs:
|
|
|
|
* Date Author Notes
|
2019-01-22 10:00:45 +08:00
|
|
|
* 2018.10.30 SummerGift first version
|
2020-03-23 15:35:27 +08:00
|
|
|
* 2019.03.05 whj4674672 add stm32h7
|
2020-10-14 15:02:23 +08:00
|
|
|
* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
|
2018-11-29 17:00:22 +08:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __DRV_USART_H__
|
|
|
|
#define __DRV_USART_H__
|
|
|
|
|
|
|
|
#include <rtthread.h>
|
|
|
|
#include "rtdevice.h"
|
|
|
|
#include <rthw.h>
|
|
|
|
#include <drv_common.h>
|
2019-01-08 11:58:57 +08:00
|
|
|
#include "drv_dma.h"
|
2018-11-29 17:00:22 +08:00
|
|
|
|
|
|
|
int rt_hw_usart_init(void);
|
|
|
|
|
2021-01-29 10:28:18 +08:00
|
|
|
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
|
2021-07-30 11:38:25 +08:00
|
|
|
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
|
2018-11-29 17:00:22 +08:00
|
|
|
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
2020-06-20 14:04:27 +08:00
|
|
|
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
|
|
|
|
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|
2018-11-29 17:00:22 +08:00
|
|
|
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
2021-01-29 10:28:18 +08:00
|
|
|
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
|
2018-11-29 17:00:22 +08:00
|
|
|
|
2021-11-01 14:56:23 +08:00
|
|
|
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \
|
|
|
|
|| defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
|
2021-11-15 10:26:14 +08:00
|
|
|
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5)
|
2018-12-26 10:43:16 +08:00
|
|
|
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
|
2020-06-20 14:04:27 +08:00
|
|
|
#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
|
|
|
|
|| defined(SOC_SERIES_STM32MP1)
|
2018-12-26 10:43:16 +08:00
|
|
|
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT
|
|
|
|
#endif
|
|
|
|
|
2022-09-22 14:13:57 +08:00
|
|
|
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
|
|
|
|
#define UART_RX_DMA_IT_HT_FLAG 0x01
|
|
|
|
#define UART_RX_DMA_IT_TC_FLAG 0x02
|
|
|
|
|
2018-11-29 17:00:22 +08:00
|
|
|
/* stm32 config class */
|
|
|
|
struct stm32_uart_config
|
|
|
|
{
|
|
|
|
const char *name;
|
|
|
|
USART_TypeDef *Instance;
|
|
|
|
IRQn_Type irq_type;
|
2019-01-08 11:58:57 +08:00
|
|
|
struct dma_config *dma_rx;
|
2019-05-03 20:52:31 +08:00
|
|
|
struct dma_config *dma_tx;
|
2018-11-29 17:00:22 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/* stm32 uart dirver class */
|
|
|
|
struct stm32_uart
|
|
|
|
{
|
|
|
|
UART_HandleTypeDef handle;
|
2019-01-08 11:58:57 +08:00
|
|
|
struct stm32_uart_config *config;
|
2020-03-23 15:35:27 +08:00
|
|
|
|
2018-12-26 10:43:16 +08:00
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
2018-11-29 17:00:22 +08:00
|
|
|
struct
|
|
|
|
{
|
|
|
|
DMA_HandleTypeDef handle;
|
2022-09-22 14:13:57 +08:00
|
|
|
rt_size_t remaining_cnt;
|
2019-05-03 20:52:31 +08:00
|
|
|
} dma_rx;
|
|
|
|
struct
|
|
|
|
{
|
|
|
|
DMA_HandleTypeDef handle;
|
|
|
|
} dma_tx;
|
2018-11-29 17:00:22 +08:00
|
|
|
#endif
|
2019-05-03 20:52:31 +08:00
|
|
|
rt_uint16_t uart_dma_flag;
|
2018-11-29 17:00:22 +08:00
|
|
|
struct rt_serial_device serial;
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif /* __DRV_USART_H__ */
|