160 lines
8.0 KiB
C
160 lines
8.0 KiB
C
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/**************************************************************************//**
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* @file eadc.c
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* @version V2.00
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* $Revision: 8 $
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* $Date: 15/08/11 10:26a $
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* @brief M451 series EADC driver source file
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*
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* @note
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* Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "M451Series.h"
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup EADC_Driver EADC Driver
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@{
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*/
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/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
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@{
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*/
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/**
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* @brief This function make EADC_module be ready to convert.
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* @param[in] eadc The pointer of the specified EADC module.
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* @param[in] u32InputMode Decides the input mode.
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* - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode.
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* - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type.
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* @return None
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* @details This function is used to set analog input mode and enable A/D Converter.
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* Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
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* @note
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*/
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void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
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{
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eadc->CTL &= (~EADC_CTL_DIFFEN_Msk);
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eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
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}
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/**
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* @brief Disable EADC_module.
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* @param[in] eadc The pointer of the specified EADC module..
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* @return None
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* @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
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*/
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void EADC_Close(EADC_T *eadc)
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{
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eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
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}
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/**
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* @brief Configure the sample control logic module.
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* @param[in] eadc The pointer of the specified EADC module.
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* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
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* @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
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* - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
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* - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger
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* - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger
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* - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger
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* - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger
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* - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger
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* - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
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* - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
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* - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
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* - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
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* - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger
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* - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger
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* - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger
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* - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger
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* - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger
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* - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger
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* - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger
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* - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger
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* - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger
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* - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger
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* - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger
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* - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger
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* @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
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* @return None
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* @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
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* sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
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*/
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void EADC_ConfigSampleModule(EADC_T *eadc, \
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uint32_t u32ModuleNum, \
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uint32_t u32TriggerSrc, \
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uint32_t u32Channel)
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{
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eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
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eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
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}
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/**
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* @brief Set trigger delay time.
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* @param[in] eadc The pointer of the specified EADC module.
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* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
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* @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
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* @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
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* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1
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* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2
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* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4
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* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16
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* @return None
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* @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
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* Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
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*/
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void EADC_SetTriggerDelayTime(EADC_T *eadc, \
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uint32_t u32ModuleNum, \
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uint32_t u32TriggerDelayTime, \
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uint32_t u32DelayClockDivider)
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{
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eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
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eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
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}
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/**
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* @brief Set ADC internal sample time.
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* @param[in] eadc The pointer of the specified EADC module.
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* @param[in] u32SampleTime Decides the internal sampling time, the range is from 1~8 ADC clock. Valid value are from 1 to 8.
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* @return None
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* @details When A/D operation at high ADC clock rate, the sampling time of analog input voltage may not enough
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* if the analog channel has heavy loading to cause fully charge time is longer.
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* User can set SMPTSEL (EADC_CTL[18:16]) to select the sampling cycle in ADC.
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*/
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void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime)
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{
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eadc->CTL &= ~EADC_CTL_SMPTSEL_Msk;
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eadc->CTL |= (u32SampleTime - 1) << EADC_CTL_SMPTSEL_Pos;
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}
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/**
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* @brief Set ADC extend sample time.
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* @param[in] eadc The pointer of the specified EADC module.
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* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
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* @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
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* @return None
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* @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
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* user can extend A/D sampling time after trigger source is coming to get enough sampling time.
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*/
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void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
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{
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eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
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eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
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}
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/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group EADC_Driver */
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/*@}*/ /* end of group Standard_Driver */
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/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
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