258 lines
7.7 KiB
C
258 lines
7.7 KiB
C
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/*
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* Copyright (c) 2021 hpmicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include "hpm_common.h"
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#include "hpm_soc.h"
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/********************** MCAUSE exception types **************************************/
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#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */
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#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */
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#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */
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#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */
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#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */
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#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */
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#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */
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#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */
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#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */
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#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */
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#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */
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#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */
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#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */
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#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_COP 12
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#define IRQ_HOST 13
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__attribute__((weak)) void mchtmr_isr(void)
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{
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}
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__attribute__((weak)) void swi_isr(void)
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{
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}
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__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3)
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{
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}
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__attribute__((weak)) long exception_handler(long cause, long epc)
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{
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switch (cause) {
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case MCAUSE_INSTR_ADDR_MISALIGNED:
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break;
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case MCAUSE_INSTR_ACCESS_FAULT:
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break;
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case MCAUSE_ILLEGAL_INSTR:
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break;
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case MCAUSE_BREAKPOINT:
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break;
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case MCAUSE_LOAD_ADDR_MISALIGNED:
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break;
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case MCAUSE_LOAD_ACCESS_FAULT:
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break;
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case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
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break;
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case MCAUSE_STORE_AMO_ACCESS_FAULT:
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break;
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case MCAUSE_ECALL_FROM_USER_MODE:
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break;
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case MCAUSE_ECALL_FROM_SUPERVISOR_MODE:
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break;
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case MCAUSE_ECALL_FROM_MACHINE_MODE:
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break;
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case MCAUSE_INSTR_PAGE_FAULT:
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break;
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case MCAUSE_LOAD_PAGE_FAULT:
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break;
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case MCAUSE_STORE_AMO_PAGE_FAULT:
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break;
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default:
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break;
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}
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/* Unhandled Trap */
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return epc;
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}
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__attribute__((weak)) long exception_s_handler(long cause, long epc)
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{
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return epc;
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}
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__attribute__((weak)) void swi_s_isr(void)
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{
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}
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__attribute__((weak)) void mchtmr_s_isr(void)
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{
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}
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#ifndef CONFIG_FREERTOS
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void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
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#else
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void irq_handler_trap(void) __attribute__ ((section(".isr_vector")));
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#endif
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void irq_handler_trap(void)
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{
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long mcause = read_csr(CSR_MCAUSE);
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long mepc = read_csr(CSR_MEPC);
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long mstatus = read_csr(CSR_MSTATUS);
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#if SUPPORT_PFT_ARCH
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long mxstatus = read_csr(CSR_MXSTATUS);
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#endif
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#ifdef __riscv_dsp
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int ucode = read_csr(CSR_UCODE);
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#endif
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#ifdef __riscv_flen
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int fcsr = read_fcsr();
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#endif
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/* clobbers list for ecall */
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#ifdef __riscv_32e
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__asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
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#else
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__asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
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#endif
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/* Do your trap handling */
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if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) {
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/* Machine timer interrupt */
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mchtmr_isr();
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}
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#ifdef USE_NONVECTOR_MODE
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else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) {
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typedef void(*isr_func_t)(void);
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/* Machine-level interrupt from PLIC */
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uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE);
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if (irq_index) {
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/* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */
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#ifndef DISABLE_IRQ_PREEMPTIVE
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enable_global_irq(CSR_MSTATUS_MIE_MASK);
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#endif
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((isr_func_t)__vector_table[irq_index])();
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__plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index);
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}
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}
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#endif
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else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) {
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/* Machine SWI interrupt */
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swi_isr();
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intc_m_complete_swi();
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} else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) {
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/* Machine Syscal call */
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__asm volatile(
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"mv a4, a3\n"
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"mv a3, a2\n"
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"mv a2, a1\n"
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"mv a1, a0\n"
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#ifdef __riscv_32e
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"mv a0, t0\n"
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#else
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"mv a0, a7\n"
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#endif
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"jalr %0\n"
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: :"r"(syscall_handler) : "a4"
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);
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mepc += 4;
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} else {
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mepc = exception_handler(mcause, mepc);
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}
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/* Restore CSR */
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write_csr(CSR_MSTATUS, mstatus);
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write_csr(CSR_MEPC, mepc);
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#if SUPPORT_PFT_ARCH
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write_csr(CSR_MXSTATUS, mxstatus);
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#endif
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#ifdef __riscv_dsp
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write_csr(CSR_UCODE, ucode);
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#endif
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#ifdef __riscv_flen
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write_fcsr(fcsr);
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#endif
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}
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#ifndef CONFIG_FREERTOS
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void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4)));
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#else
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void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector")));
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#endif
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void irq_handler_s_trap(void)
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{
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long scause = read_csr(CSR_SCAUSE);
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long sepc = read_csr(CSR_SEPC);
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long sstatus = read_csr(CSR_SSTATUS);
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/* clobbers list for ecall */
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#ifdef __riscv_32e
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__asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
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#else
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__asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
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#endif
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/* Do your trap handling */
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if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) {
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/* Machine timer interrupt */
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mchtmr_s_isr();
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}
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#ifdef USE_NONVECTOR_MODE
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else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) {
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typedef void(*isr_func_t)(void);
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/* Machine-level interrupt from PLIC */
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uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE);
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#ifndef DISABLE_IRQ_PREEMPTIVE
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enable_s_global_irq(CSR_SSTATUS_SIE_MASK);
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#endif
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((isr_func_t)__vector_s_table[irq_index])();
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__plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index);
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}
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#endif
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else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) {
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/* Machine SWI interrupt */
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intc_m_claim_swi();
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swi_s_isr();
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intc_s_complete_swi();
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} else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) {
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/* Machine Syscal call */
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__asm volatile(
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"mv a4, a3\n"
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"mv a3, a2\n"
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"mv a2, a1\n"
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"mv a1, a0\n"
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#ifdef __riscv_32e
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"mv a0, t0\n"
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#else
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"mv a0, a7\n"
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#endif
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"jalr %0\n"
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: :"r"(syscall_handler) : "a4"
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);
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sepc += 4;
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} else {
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sepc = exception_s_handler(scause, sepc);
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}
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/* Restore CSR */
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write_csr(CSR_SSTATUS, sstatus);
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write_csr(CSR_SEPC, sepc);
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}
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