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rt-thread/bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.c

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add tkm32f499 bsp
2021-10-14 18:50:35 +08:00
#include "sys.h"
#include "HAL_misc.h"
void RemapVtorTable(void)
{
int i;
RCC->AHB1ENR |= 1<<13;//bkp clk,enable sram
//<2F><>ROM<4F><4D><EFBFBD>ж<EFBFBD>
for(i = 0;i<90;i++)
{
NVIC_DisableIRQ((IRQn_Type)i);
}
SCB->VTOR = 0;
SCB->VTOR |= 0x1<<29;
for(i = 0;i < 512;i+=4)
*(u32*)(T_SRAM_BASE + i) = *(u32*)(T_SDRAM_BASE+i);
}
void AI_Responder_enable(void)
{
AI_Responder->ADDR1= 0x70807040;
// AI_Responder->ADDR0 = 0x70027080;
AI_Responder->ADDR1 = 0;
AI_Responder->CCR &= ~(0x3<<3);
AI_Responder->CCR |= 1;
while((AI_Responder->SR & 0x3) != 2);
}
void AI_Responder_disable(void)
{
AI_Responder->CCR &= ~1;
}
//<2F>ⲿ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>
//ֻ<><D6BB><EFBFBD><EFBFBD>GPIOA~E
//<2F><><EFBFBD><EFBFBD>:
//GPIOx:0~4,<2C><><EFBFBD><EFBFBD>GPIOA~E
//BITx:<3A><>Ҫʹ<D2AA>ܵ<EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PB12<31><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 12;
//TRIM:<3A><><EFBFBD><EFBFBD>ģʽ,1,<2C>½<EFBFBD><C2BD><EFBFBD>;2,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>;3<><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD>
//<2F>ú<EFBFBD><C3BA><EFBFBD>һ<EFBFBD><D2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31>IO<49><4F>,<2C><><EFBFBD><EFBFBD>IO<49><4F>,<2C><><EFBFBD><EFBFBD><EFBFBD>ε<EFBFBD><CEB5><EFBFBD>
//<2F>ú<EFBFBD><C3BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ж<EFBFBD>,<2C>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
{
u8 EXTOFFSET=(BITx%4)*4;
RCC->APB2ENR|=1<<14; //ʹ<><CAB9>SYSCFGʱ<47><CAB1>
SYSCFG->EXTICR[BITx/4]&=~(0x000F<<EXTOFFSET);//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>
SYSCFG->EXTICR[BITx/4]|=GPIOx<<EXTOFFSET; //EXTI.BITxӳ<78>䵽GPIOx.BITx
//<2F>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
EXTI->IMR|=1<<BITx; //<2F><><EFBFBD><EFBFBD>line BITx<54>ϵ<EFBFBD><CFB5>ж<EFBFBD>(<28><><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>ֹ<EFBFBD>жϣ<D0B6><CFA3>򷴲<EFBFBD><F2B7B4B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
if(TRIM&0x01)EXTI->FTSR|=1<<BITx; //line BITx<54>¼<EFBFBD><C2BC>½<EFBFBD><C2BD>ش<EFBFBD><D8B4><EFBFBD>
if(TRIM&0x02)EXTI->RTSR|=1<<BITx; //line BITx<54>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD>
}
//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
void WFI_SET(void)
{
__ASM volatile("wfi");
}
//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
void INTX_DISABLE(void)
{
__ASM volatile("cpsid i");
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
void INTX_ENABLE(void)
{
__ASM volatile("cpsie i");
}
//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ __set_MSP(0x70002000);
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
void Sys_Standby(void)
{
SCB->SCR|=1<<2; //ʹ<><CAB9>SLEEPDEEPλ (SYS->CTRL)
RCC->APB1ENR|=1<<28;//ʹ<>ܵ<EFBFBD>Դʱ<D4B4><CAB1>
PWR->CSR|=1<<8; //<2F><><EFBFBD><EFBFBD>WKUP<55><50><EFBFBD>ڻ<EFBFBD><DABB><EFBFBD>
PWR->CR|=1<<2; //<2F><><EFBFBD><EFBFBD>Wake-up <20><>־
PWR->CR|=1<<1; //PDDS<44><53>λ
WFI_SET(); //ִ<><D6B4>WFIָ<49><D6B8>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
}
//ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>λ
void Sys_Soft_Reset(void)
{
SCB->AIRCR =0X05FA0000|(u32)0x04;
}
// TK499_NVIC_Init(2,2,TK80_IRQn,2);
//<2F><><EFBFBD><EFBFBD>NVIC
//NVIC_PreemptionPriority:<3A><>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>
//NVIC_SubPriority :<3A><>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
//NVIC_Channel :<3A>жϱ<D0B6><CFB1><EFBFBD>
//NVIC_Group :<3A>жϷ<D0B6><CFB7><EFBFBD> 0~4
//ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD>ܳ<EFBFBD><DCB3><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Χ!<21><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>벻<EFBFBD><EBB2BB><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
//<2F>黮<EFBFBD><E9BBAE>:
//<2F><>0:0λ<30><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,4λ<34><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
//<2F><>1:1λ<31><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,3λ<33><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
//<2F><>2:2λ<32><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,2λ<32><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
//<2F><>3:3λ<33><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,1λ<31><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
//<2F><>4:4λ<34><CEBB>ռ<EFBFBD><D5BC><EFBFBD>ȼ<EFBFBD>,0λ<30><CEBB>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD>
//NVIC_SubPriority<74><79>NVIC_PreemptionPriority<74><79>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD>,<2C><>ֵԽС,Խ<><D4BD><EFBFBD><EFBFBD>
void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
{
u32 temp;
NVIC_SetPriorityGrouping(NVIC_Group);//<2F><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD>
temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
temp&=0xf; //ȡ<><C8A1><EFBFBD><EFBFBD>λ
NVIC->ISER[NVIC_Channel/32]|=1<<NVIC_Channel%32;//ʹ<><CAB9><EFBFBD>ж<EFBFBD>λ(Ҫ<><D2AA><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ICER<45><52>ӦλΪ1<CEAA><31><EFBFBD><EFBFBD>)
NVIC->IP[NVIC_Channel]|=temp<<4; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>
}
void TK80_IRQHandler(void)
{
if(TK80->SR & 0x1)
{
}
if(TK80->SR & 0x2)
{
}
if(TK80->SR & 0x4)
{
}
if(TK80->SR & 0x8)
{
}
TK80->SR |= 0;
}
//<2F><><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>
//#define T_SRAM_FUN1 0x20000400
//copyAtoB((u32)LCD_PutPixel&0xFFFFFFFE,T_SRAM_FUN1,800);//<2F><><EFBFBD>غ<EFBFBD><D8BA><EFBFBD><EFBFBD><EFBFBD>SRAM
//void copyAtoB(u32 srcAdd,u32 dstAdd,u16 len)
//{
// len = (len + 3)/4;
// while(len--)
// {
// *(u32*)dstAdd = *(u32*)srcAdd;
// dstAdd += 4 ;
// srcAdd +=4 ;
// }
//}