2022-07-05 16:45:32 +08:00
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/*
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2023-01-20 10:49:23 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2022-07-05 16:45:32 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-04 Rbb666 first version
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*/
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#include "drv_common.h"
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#include "drv_adc.h"
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#include "cyhal.h"
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#include "cybsp.h"
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#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
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//#define DRV_DEBUG
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#define LOG_TAG "drv.adc"
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#include <drv_log.h>
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#define VPLUS_CHANNEL_0 (P10_0)
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struct ifx_adc
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{
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struct rt_adc_device ifx_adc_device;
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cyhal_adc_channel_t *adc_ch;
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char *name;
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};
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static struct ifx_adc ifx_adc_obj[] =
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{
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2022-07-27 15:41:25 +08:00
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#ifdef BSP_USING_ADC1
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2022-07-05 16:45:32 +08:00
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ADC1_CONFIG,
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2022-07-27 15:41:25 +08:00
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#endif
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2022-07-05 16:45:32 +08:00
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};
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static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
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{
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cyhal_adc_channel_t *adc_ch;
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cy_rslt_t result;
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RT_ASSERT(device != RT_NULL);
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adc_ch = device->parent.user_data;
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const cyhal_adc_channel_config_t channel_config =
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{
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.enable_averaging = false, // Disable averaging for channel
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.min_acquisition_ns = 1000, // Minimum acquisition time set to 1us
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.enabled = enabled // Sample this channel when ADC performs a scan
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};
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if (enabled)
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{
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/* Initialize ADC. The ADC block which can connect to pin 10[0] is selected */
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result = cyhal_adc_init(&adc_obj, VPLUS_CHANNEL_0, NULL);
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2022-07-27 15:41:25 +08:00
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2022-07-05 16:45:32 +08:00
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if (result != RT_EOK)
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{
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2023-04-04 20:51:43 +08:00
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LOG_E("ADC initialization failed. Error: %llu\n", (long unsigned int)result);
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2022-07-05 16:45:32 +08:00
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return -RT_ENOSYS;
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}
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/* Initialize a channel 0 and configure it to scan P10_0 in single ended mode. */
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result = cyhal_adc_channel_init_diff(adc_ch, &adc_obj, VPLUS_CHANNEL_0,
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CYHAL_ADC_VNEG, &channel_config);
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2022-07-27 15:41:25 +08:00
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2022-07-05 16:45:32 +08:00
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if (result != RT_EOK)
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{
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2023-04-04 20:51:43 +08:00
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LOG_E("ADC single ended channel initialization failed. Error: %llu\n", (long unsigned int)result);
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2022-07-05 16:45:32 +08:00
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return -RT_ENOSYS;
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}
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/* Update ADC configuration */
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result = cyhal_adc_configure(&adc_obj, &adc_config);
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2022-07-27 15:41:25 +08:00
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2022-07-05 16:45:32 +08:00
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if (result != RT_EOK)
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{
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2023-04-04 20:51:43 +08:00
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printf("ADC configuration update failed. Error: %llu\n", (long unsigned int)result);
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2022-07-05 16:45:32 +08:00
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return -RT_ENOSYS;
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}
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}
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else
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{
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cyhal_adc_free(&adc_obj);
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cyhal_adc_channel_free(adc_ch);
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}
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return RT_EOK;
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}
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static rt_err_t ifx_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
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{
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cyhal_adc_channel_t *adc_ch;
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RT_ASSERT(device != RT_NULL);
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adc_ch = device->parent.user_data;
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channel = adc_ch->channel_idx;
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*value = cyhal_adc_read(adc_ch);
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return RT_EOK;
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}
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static const struct rt_adc_ops at_adc_ops =
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{
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.enabled = ifx_adc_enabled,
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.convert = ifx_get_adc_value,
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};
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static int rt_hw_adc_init(void)
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{
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int result = RT_EOK;
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int i = 0;
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for (i = 0; i < sizeof(ifx_adc_obj) / sizeof(ifx_adc_obj[0]); i++)
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{
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/* register ADC device */
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if (rt_hw_adc_register(&ifx_adc_obj[i].ifx_adc_device, ifx_adc_obj[i].name, &at_adc_ops, ifx_adc_obj[i].adc_ch) == RT_EOK)
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{
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LOG_D("%s register success", at32_adc_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", ifx_adc_obj[i].name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_adc_init);
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#endif /* BSP_USING_ADC */
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