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/*!
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2021-06-09 16:24:20 +08:00
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\file gd32f4xx_ipa.h
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\brief definitions for the IPA
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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2017-08-22 15:52:57 +08:00
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*/
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/*
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2021-06-09 16:24:20 +08:00
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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2017-08-22 15:52:57 +08:00
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*/
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#ifndef GD32F4XX_IPA_H
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#define GD32F4XX_IPA_H
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#include "gd32f4xx.h"
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/* TLI definitions */
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#define IPA IPA_BASE /*!< IPA base address */
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/* bits definitions */
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/* registers definitions */
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#define IPA_CTL REG32(IPA + 0x00U) /*!< IPA control register */
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#define IPA_INTF REG32(IPA + 0x04U) /*!< IPA interrupt flag register */
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#define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */
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#define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */
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#define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */
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#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */
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#define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */
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#define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */
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#define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */
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#define IPA_BPCTL REG32(IPA + 0x24U) /*!< IPA background pixel control register */
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#define IPA_BPV REG32(IPA + 0x28U) /*!< IPA background pixel value register */
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#define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */
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#define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */
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#define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */
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#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */
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#define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */
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#define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */
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#define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */
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#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */
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#define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */
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/* IPA_CTL */
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#define IPA_CTL_TEN BIT(0) /*!< transfer enable */
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#define IPA_CTL_THU BIT(1) /*!< transfer hang up */
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#define IPA_CTL_TST BIT(2) /*!< transfer stop */
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#define IPA_CTL_TAEIE BIT(8) /*!< enable bit for transfer access error interrupt */
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#define IPA_CTL_FTFIE BIT(9) /*!< enable bit for full transfer finish interrup */
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#define IPA_CTL_TLMIE BIT(10) /*!< enable bit for transfer line mark interrupt */
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#define IPA_CTL_LACIE BIT(11) /*!< enable bit for LUT access conflict interrupt */
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#define IPA_CTL_LLFIE BIT(12) /*!< enable bit for LUT loading finish interrupt */
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#define IPA_CTL_WCFIE BIT(13) /*!< enable bit for wrong configuration interrupt */
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#define IPA_CTL_PFCM BITS(16,17) /*!< pixel format convert mode */
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/* IPA_INTF */
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#define IPA_INTF_TAEIF BIT(0) /*!< transfer access error interrupt flag */
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#define IPA_INTF_FTFIF BIT(1) /*!< full transfer finish interrupt flag */
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#define IPA_INTF_TLMIF BIT(2) /*!< transfer line mark interrupt flag */
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#define IPA_INTF_LACIF BIT(3) /*!< LUT access conflict interrupt flag */
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#define IPA_INTF_LLFIF BIT(4) /*!< LUT loading finish interrupt flag */
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#define IPA_INTF_WCFIF BIT(5) /*!< wrong configuration interrupt flag */
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/* IPA_INTC */
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#define IPA_INTC_TAEIFC BIT(0) /*!< clear bit for transfer access error interrupt flag */
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#define IPA_INTC_FTFIFC BIT(1) /*!< clear bit for full transfer finish interrupt flag */
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#define IPA_INTC_TLMIFC BIT(2) /*!< clear bit for transfer line mark interrupt flag */
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#define IPA_INTC_LACIFC BIT(3) /*!< clear bit for LUT access conflict interrupt flag */
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#define IPA_INTC_LLFIFC BIT(4) /*!< clear bit for LUT loading finish interrupt flag */
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#define IPA_INTC_WCFIFC BIT(5) /*!< clear bit for wrong configuration interrupt flag */
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/* IPA_FMADDR */
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#define IPA_FMADDR_FMADDR BITS(0,31) /*!< foreground memory base address */
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/* IPA_FLOFF */
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#define IPA_FLOFF_FLOFF BITS(0,13) /*!< foreground line offset */
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/* IPA_BMADDR */
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#define IPA_BMADDR_BMADDR BITS(0,31) /*!< background memory base address */
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/* IPA_BLOFF */
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#define IPA_BLOFF_BLOFF BITS(0,13) /*!< background line offset */
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/* IPA_FPCTL */
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#define IPA_FPCTL_FPF BITS(0,3) /*!< foreground pixel format */
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#define IPA_FPCTL_FLPF BIT(4) /*!< foreground LUT pixel format */
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#define IPA_FPCTL_FLLEN BIT(5) /*!< foreground LUT loading enable */
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#define IPA_FPCTL_FCNP BITS(8,15) /*!< foreground LUT number of pixel */
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#define IPA_FPCTL_FAVCA BITS(16,17) /*!< foreground alpha value calculation algorithm */
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#define IPA_FPCTL_FPDAV BITS(24,31) /*!< foreground pre- defined alpha value */
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/* IPA_FPV */
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#define IPA_FPV_FPDBV BITS(0,7) /*!< foreground pre-defined red value */
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#define IPA_FPV_FPDGV BITS(8,15) /*!< foreground pre-defined green value */
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#define IPA_FPV_FPDRV BITS(16,23) /*!< foreground pre-defined red value */
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/* IPA_BPCTL */
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#define IPA_BPCTL_BPF BITS(0,3) /*!< background pixel format */
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#define IPA_BPCTL_BLPF BIT(4) /*!< background LUT pixel format */
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#define IPA_BPCTL_BLLEN BIT(5) /*!< background LUT loading enable */
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#define IPA_BPCTL_BCNP BITS(8,15) /*!< background LUT number of pixel */
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#define IPA_BPCTL_BAVCA BITS(16,17) /*!< background alpha value calculation algorithm */
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#define IPA_BPCTL_BPDAV BITS(24,31) /*!< background pre- defined alpha value */
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/* IPA_BPV */
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#define IPA_BPV_BPDBV BITS(0,7) /*!< background pre-defined blue value */
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#define IPA_BPV_BPDGV BITS(8,15) /*!< background pre-defined green value */
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#define IPA_BPV_BPDRV BITS(16,23) /*!< background pre-defined red value */
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/* IPA_FLMADDR */
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#define IPA_FLMADDR_FLMADDR BITS(0,31) /*!< foreground LUT memory base address */
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/* IPA_BLMADDR */
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#define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */
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/* IPA_DPCTL */
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#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */
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/* IPA_DPV */
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/* destination pixel format ARGB8888 */
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#define IPA_DPV_DPDBV_0 BITS(0,7) /*!< destination pre-defined blue value */
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#define IPA_DPV_DPDGV_0 BITS(8,15) /*!< destination pre-defined green value */
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#define IPA_DPV_DPDRV_0 BITS(16,23) /*!< destination pre-defined red value */
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#define IPA_DPV_DPDAV_0 BITS(24,31) /*!< destination pre-defined alpha value */
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/* destination pixel format RGB8888 */
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#define IPA_DPV_DPDBV_1 BITS(0,7) /*!< destination pre-defined blue value */
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#define IPA_DPV_DPDGV_1 BITS(8,15) /*!< destination pre-defined green value */
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#define IPA_DPV_DPDRV_1 BITS(16,23) /*!< destination pre-defined red value */
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/* destination pixel format RGB565 */
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#define IPA_DPV_DPDBV_2 BITS(0,4) /*!< destination pre-defined blue value */
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#define IPA_DPV_DPDGV_2 BITS(5,10) /*!< destination pre-defined green value */
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#define IPA_DPV_DPDRV_2 BITS(11,15) /*!< destination pre-defined red value */
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/* destination pixel format ARGB1555 */
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#define IPA_DPV_DPDBV_3 BITS(0,4) /*!< destination pre-defined blue value */
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#define IPA_DPV_DPDGV_3 BITS(5,9) /*!< destination pre-defined green value */
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#define IPA_DPV_DPDRV_3 BITS(10,14) /*!< destination pre-defined red value */
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#define IPA_DPV_DPDAV_3 BIT(15) /*!< destination pre-defined alpha value */
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/* destination pixel format ARGB4444 */
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#define IPA_DPV_DPDBV_4 BITS(0,3) /*!< destination pre-defined blue value */
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#define IPA_DPV_DPDGV_4 BITS(4,7) /*!< destination pre-defined green value */
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#define IPA_DPV_DPDRV_4 BITS(8,11) /*!< destination pre-defined red value */
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#define IPA_DPV_DPDAV_4 BITS(12,15) /*!< destination pre-defined alpha value */
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/* IPA_DMADDR */
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#define IPA_DMADDR_DMADDR BITS(0,31) /*!< destination memory base address */
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/* IPA_DLOFF */
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#define IPA_DLOFF_DLOFF BITS(0,13) /*!< destination line offset */
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/* IPA_IMS */
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#define IPA_IMS_HEIGHT BITS(0,15) /*!< height of the image to be processed */
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#define IPA_IMS_WIDTH BITS(16,29) /*!< width of the image to be processed */
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/* IPA_LM */
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#define IPA_LM_LM BITS(0,15) /*!< line mark */
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/* IPA_ITCTL */
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#define IPA_ITCTL_ITEN BIT(0) /*!< inter-timer enable */
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#define IPA_ITCTL_NCCI BITS(8,15) /*!< number of clock cycles interval */
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/* constants definitions */
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/* IPA foreground parameter struct definitions */
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typedef struct
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{
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uint32_t foreground_memaddr; /*!< foreground memory base address */
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uint32_t foreground_lineoff; /*!< foreground line offset */
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uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */
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uint32_t foreground_alpha_algorithm; /*!< foreground alpha value calculation algorithm */
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uint32_t foreground_pf; /*!< foreground pixel format */
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uint32_t foreground_prered; /*!< foreground pre-defined red value */
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uint32_t foreground_pregreen; /*!< foreground pre-defined green value */
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uint32_t foreground_preblue; /*!< foreground pre-defined blue value */
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}ipa_foreground_parameter_struct;
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/* IPA background parameter struct definitions */
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typedef struct
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{
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uint32_t background_memaddr; /*!< background memory base address */
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uint32_t background_lineoff; /*!< background line offset */
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uint32_t background_prealpha; /*!< background pre-defined alpha value */
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uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */
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uint32_t background_pf; /*!< background pixel format */
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uint32_t background_prered; /*!< background pre-defined red value */
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uint32_t background_pregreen; /*!< background pre-defined green value */
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uint32_t background_preblue; /*!< background pre-defined blue value */
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}ipa_background_parameter_struct;
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/* IPA destination parameter struct definitions */
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typedef struct
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{
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uint32_t destination_memaddr; /*!< destination memory base address */
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uint32_t destination_lineoff; /*!< destination line offset */
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uint32_t destination_prealpha; /*!< destination pre-defined alpha value */
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uint32_t destination_pf; /*!< destination pixel format */
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uint32_t destination_prered; /*!< destination pre-defined red value */
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uint32_t destination_pregreen; /*!< destination pre-defined green value */
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uint32_t destination_preblue; /*!< destination pre-defined blue value */
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uint32_t image_width; /*!< width of the image to be processed */
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uint32_t image_height; /*!< height of the image to be processed */
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}ipa_destination_parameter_struct;
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/* destination pixel format */
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typedef enum
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{
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IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */
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IPA_DPF_RGB888, /*!< destination pixel format RGB888 */
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IPA_DPF_RGB565, /*!< destination pixel format RGB565 */
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IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */
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IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */
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} ipa_dpf_enum;
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/* LUT pixel format */
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#define IPA_LUT_PF_ARGB8888 ((uint8_t)0x00U) /*!< LUT pixel format ARGB8888 */
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#define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */
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/* Inter-timer */
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#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */
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#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */
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/* IPA pixel format convert mode */
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#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
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#define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */
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#define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */
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#define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */
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#define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */
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/* foreground alpha value calculation algorithm */
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2021-06-09 16:24:20 +08:00
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#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
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2017-08-22 15:52:57 +08:00
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#define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */
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#define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */
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#define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */
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/* background alpha value calculation algorithm */
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2021-06-09 16:24:20 +08:00
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#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
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2017-08-22 15:52:57 +08:00
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#define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */
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#define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */
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#define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */
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/* foreground pixel format */
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2021-06-09 16:24:20 +08:00
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#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
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2017-08-22 15:52:57 +08:00
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#define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */
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#define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */
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#define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */
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#define FOREGROUND_PPF_ARG1555 FPCTL_PPF(3) /*!< foreground pixel format ARGB1555 */
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#define FOREGROUND_PPF_ARGB4444 FPCTL_PPF(4) /*!< foreground pixel format ARGB4444 */
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#define FOREGROUND_PPF_L8 FPCTL_PPF(5) /*!< foreground pixel format L8 */
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#define FOREGROUND_PPF_AL44 FPCTL_PPF(6) /*!< foreground pixel format AL44 */
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#define FOREGROUND_PPF_AL88 FPCTL_PPF(7) /*!< foreground pixel format AL88 */
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#define FOREGROUND_PPF_L4 FPCTL_PPF(8) /*!< foreground pixel format L4 */
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#define FOREGROUND_PPF_A8 FPCTL_PPF(9) /*!< foreground pixel format A8 */
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#define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */
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/* background pixel format */
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2021-06-09 16:24:20 +08:00
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#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
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2017-08-22 15:52:57 +08:00
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#define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */
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#define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */
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#define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */
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#define BACKGROUND_PPF_ARG1555 BPCTL_PPF(3) /*!< background pixel format ARGB1555 */
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#define BACKGROUND_PPF_ARGB4444 BPCTL_PPF(4) /*!< background pixel format ARGB4444 */
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#define BACKGROUND_PPF_L8 BPCTL_PPF(5) /*!< background pixel format L8 */
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#define BACKGROUND_PPF_AL44 BPCTL_PPF(6) /*!< background pixel format AL44 */
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#define BACKGROUND_PPF_AL88 BPCTL_PPF(7) /*!< background pixel format AL88 */
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#define BACKGROUND_PPF_L4 BPCTL_PPF(8) /*!< background pixel format L4 */
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#define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */
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#define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */
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2021-06-09 16:24:20 +08:00
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/* IPA flags */
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#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
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#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
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#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
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#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
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#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
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#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
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/* IPA interrupt enable or disable */
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#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */
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#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */
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#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */
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#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */
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#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */
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#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */
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/* IPA interrupt flags */
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#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
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#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
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#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
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#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
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#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
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#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
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2017-08-22 15:52:57 +08:00
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/* function declarations */
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2021-06-09 16:24:20 +08:00
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/* functions enable or disable, pixel format convert mode set */
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2017-08-22 15:52:57 +08:00
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/* deinitialize IPA */
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void ipa_deinit(void);
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2021-06-09 16:24:20 +08:00
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/* enable IPA transfer */
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2017-08-22 15:52:57 +08:00
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void ipa_transfer_enable(void);
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2021-06-09 16:24:20 +08:00
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/* enable IPA transfer hang up */
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2017-08-22 15:52:57 +08:00
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void ipa_transfer_hangup_enable(void);
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2021-06-09 16:24:20 +08:00
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/* disable IPA transfer hang up */
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2017-08-22 15:52:57 +08:00
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void ipa_transfer_hangup_disable(void);
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2021-06-09 16:24:20 +08:00
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/* enable IPA transfer stop */
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2017-08-22 15:52:57 +08:00
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void ipa_transfer_stop_enable(void);
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2021-06-09 16:24:20 +08:00
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/* disable IPA transfer stop */
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2017-08-22 15:52:57 +08:00
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void ipa_transfer_stop_disable(void);
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2021-06-09 16:24:20 +08:00
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/* enable IPA foreground LUT loading */
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2017-08-22 15:52:57 +08:00
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void ipa_foreground_lut_loading_enable(void);
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2021-06-09 16:24:20 +08:00
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/* enable IPA background LUT loading */
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2017-08-22 15:52:57 +08:00
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void ipa_background_lut_loading_enable(void);
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2021-06-09 16:24:20 +08:00
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/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */
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void ipa_pixel_format_convert_mode_set(uint32_t pfcm);
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2017-08-22 15:52:57 +08:00
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2021-06-09 16:24:20 +08:00
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/* structure initialization, foreground, background, destination and LUT initialization */
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/* initialize the structure of IPA foreground parameter struct with the default values, it is
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suggested that call this function after an ipa_foreground_parameter_struct structure is defined */
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void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct);
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2017-08-22 15:52:57 +08:00
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/* initialize foreground parameters */
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void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct);
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2021-06-09 16:24:20 +08:00
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/* initialize the structure of IPA background parameter struct with the default values, it is
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suggested that call this function after an ipa_background_parameter_struct structure is defined */
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void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct);
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2017-08-22 15:52:57 +08:00
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/* initialize background parameters */
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void ipa_background_init(ipa_background_parameter_struct* background_struct);
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2021-06-09 16:24:20 +08:00
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/* initialize the structure of IPA destination parameter struct with the default values, it is
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suggested that call this function after an ipa_destination_parameter_struct structure is defined */
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void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct);
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2017-08-22 15:52:57 +08:00
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/* initialize destination parameters */
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void ipa_destination_init(ipa_destination_parameter_struct* destination_struct);
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/* initialize IPA foreground LUT parameters */
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2021-06-09 16:24:20 +08:00
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void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr);
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2017-08-22 15:52:57 +08:00
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/* initialize IPA background LUT parameters */
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2021-06-09 16:24:20 +08:00
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void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr);
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/* configuration functions */
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/* configure IPA line mark */
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void ipa_line_mark_config(uint16_t line_num);
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/* inter-timer enable or disable */
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void ipa_inter_timer_config(uint8_t timer_cfg);
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/* configure the number of clock cycles interval */
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void ipa_interval_clock_num_config(uint8_t clk_num);
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/* flag and interrupt functions */
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/* get IPA flag status in IPA_INTF register */
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FlagStatus ipa_flag_get(uint32_t flag);
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/* clear IPA flag in IPA_INTF register */
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void ipa_flag_clear(uint32_t flag);
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/* enable IPA interrupt */
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void ipa_interrupt_enable(uint32_t int_flag);
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/* disable IPA interrupt */
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void ipa_interrupt_disable(uint32_t int_flag);
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2017-08-22 15:52:57 +08:00
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/* get IPA interrupt flag */
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2021-06-09 16:24:20 +08:00
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FlagStatus ipa_interrupt_flag_get(uint32_t int_flag);
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2017-08-22 15:52:57 +08:00
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/* clear IPA interrupt flag */
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2021-06-09 16:24:20 +08:00
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void ipa_interrupt_flag_clear(uint32_t int_flag);
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2017-08-22 15:52:57 +08:00
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#endif /* GD32F4XX_IPA_H */
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