235 lines
6.7 KiB
C
235 lines
6.7 KiB
C
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/*
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* File : mips_cache.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016<EFBFBD><EFBFBD>9<EFBFBD><EFBFBD>10<EFBFBD><EFBFBD> Urey the first version
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*/
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#ifndef _MIPS_CACHE_H_
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#define _MIPS_CACHE_H_
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#ifndef __ASSEMBLER__
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#include <rtdef.h>
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#include <mips_cfg.h>
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/*
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* Cache Operations available on all MIPS processors with R4000-style caches
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*/
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#define INDEX_INVALIDATE_I 0x00
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#define INDEX_WRITEBACK_INV_D 0x01
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#define INDEX_LOAD_TAG_I 0x04
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#define INDEX_LOAD_TAG_D 0x05
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#define INDEX_STORE_TAG_I 0x08
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#define INDEX_STORE_TAG_D 0x09
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#if defined(CONFIG_CPU_LOONGSON2)
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#define HIT_INVALIDATE_I 0x00
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#else
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#define HIT_INVALIDATE_I 0x10
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#endif
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#define HIT_INVALIDATE_D 0x11
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#define HIT_WRITEBACK_INV_D 0x15
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/*
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*The lock state is cleared by executing an Index
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Invalidate, Index Writeback Invalidate, Hit
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Invalidate, or Hit Writeback Invalidate
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operation to the locked line, or via an Index
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Store Tag operation with the lock bit reset in
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the TagLo register.
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*/
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#define FETCH_AND_LOCK_I 0x1c
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#define FETCH_AND_LOCK_D 0x1d
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enum dma_data_direction
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{
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DMA_BIDIRECTIONAL = 0,
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DMA_TO_DEVICE = 1,
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DMA_FROM_DEVICE = 2,
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DMA_NONE = 3,
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};
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/*
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* R4000-specific cacheops
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*/
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#define CREATE_DIRTY_EXCL_D 0x0d
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#define FILL 0x14
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#define HIT_WRITEBACK_I 0x18
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#define HIT_WRITEBACK_D 0x19
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/*
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* R4000SC and R4400SC-specific cacheops
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*/
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#define INDEX_INVALIDATE_SI 0x02
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#define INDEX_WRITEBACK_INV_SD 0x03
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#define INDEX_LOAD_TAG_SI 0x06
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#define INDEX_LOAD_TAG_SD 0x07
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#define INDEX_STORE_TAG_SI 0x0A
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#define INDEX_STORE_TAG_SD 0x0B
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#define CREATE_DIRTY_EXCL_SD 0x0f
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#define HIT_INVALIDATE_SI 0x12
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#define HIT_INVALIDATE_SD 0x13
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#define HIT_WRITEBACK_INV_SD 0x17
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#define HIT_WRITEBACK_SD 0x1b
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#define HIT_SET_VIRTUAL_SI 0x1e
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#define HIT_SET_VIRTUAL_SD 0x1f
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/*
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* R5000-specific cacheops
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*/
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#define R5K_PAGE_INVALIDATE_S 0x17
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/*
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* RM7000-specific cacheops
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*/
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#define PAGE_INVALIDATE_T 0x16
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/*
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* R10000-specific cacheops
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*
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* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
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* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
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*/
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#define INDEX_WRITEBACK_INV_S 0x03
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#define INDEX_LOAD_TAG_S 0x07
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#define INDEX_STORE_TAG_S 0x0B
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#define HIT_INVALIDATE_S 0x13
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#define CACHE_BARRIER 0x14
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#define HIT_WRITEBACK_INV_S 0x17
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#define INDEX_LOAD_DATA_I 0x18
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#define INDEX_LOAD_DATA_D 0x19
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#define INDEX_LOAD_DATA_S 0x1b
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#define INDEX_STORE_DATA_I 0x1c
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#define INDEX_STORE_DATA_D 0x1d
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#define INDEX_STORE_DATA_S 0x1f
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#define cache_op(op, addr) \
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__asm__ __volatile__( \
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".set push\n" \
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".set noreorder\n" \
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".set mips3\n" \
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"cache %0, %1\n" \
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".set pop\n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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#define cache16_unroll32(base, op) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
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" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
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" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
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" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
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" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
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" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
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" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
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" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
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" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
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" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
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" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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: \
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: "r" (base), \
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"i" (op));
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static inline void flush_icache_line_indexed(rt_ubase_t addr)
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{
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cache_op(INDEX_INVALIDATE_I, addr);
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}
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static inline void flush_dcache_line_indexed(rt_ubase_t addr)
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{
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cache_op(INDEX_WRITEBACK_INV_D, addr);
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}
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static inline void flush_icache_line(rt_ubase_t addr)
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{
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cache_op(HIT_INVALIDATE_I, addr);
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}
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static inline void lock_icache_line(rt_ubase_t addr)
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{
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cache_op(FETCH_AND_LOCK_I, addr);
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}
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static inline void lock_dcache_line(rt_ubase_t addr)
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{
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cache_op(FETCH_AND_LOCK_D, addr);
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}
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static inline void flush_dcache_line(rt_ubase_t addr)
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{
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cache_op(HIT_WRITEBACK_INV_D, addr);
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}
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static inline void invalidate_dcache_line(rt_ubase_t addr)
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{
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cache_op(HIT_INVALIDATE_D, addr);
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}
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static inline void blast_dcache16(void)
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{
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rt_ubase_t start = KSEG0BASE;
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rt_ubase_t end = start + g_mips_core.dcache_size;
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rt_ubase_t addr;
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for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
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cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
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}
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static inline void inv_dcache16(void)
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{
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rt_ubase_t start = KSEG0BASE;
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rt_ubase_t end = start + g_mips_core.dcache_size;
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rt_ubase_t addr;
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for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
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cache16_unroll32(addr, HIT_INVALIDATE_D);
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}
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static inline void blast_icache16(void)
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{
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rt_ubase_t start = KSEG0BASE;
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rt_ubase_t end = start + g_mips_core.icache_size;
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rt_ubase_t addr;
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for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
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cache16_unroll32(addr, INDEX_INVALIDATE_I);
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}
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void r4k_cache_init(void);
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void r4k_cache_flush_all(void);
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void r4k_icache_flush_all(void);
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void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
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void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
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void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
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void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
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void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction);
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#endif
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#endif /* _MIPS_CACHE_H_ */
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