301 lines
13 KiB
C
301 lines
13 KiB
C
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ZYNQMP_UART_H__
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#define __ZYNQMP_UART_H__
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#include <zynqmp_reg.h>
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/* The following constant defines the amount of error that is allowed for
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* a specified baud rate. This error is the difference between the actual
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* baud rate that will be generated using the specified clock and the
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* desired baud rate.
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*/
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#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
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/*
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* The following constants indicate the max and min baud rates and these
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* numbers are based only on the testing that has been done. The hardware
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* is capable of other baud rates.
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*/
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#define XUARTPS_MAX_RATE 6240000U
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#define XUARTPS_MIN_RATE 110U
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/** @name Register Map
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*
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* Register offsets for the UART.
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* @{
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*/
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#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
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#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
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#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
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#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
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#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
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#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
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#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
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#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
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#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
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#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
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#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
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#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
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#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
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#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
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#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
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#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
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#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
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/* @} */
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/** @name Control Register
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*
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* The Control register (CR) controls the major functions of the device.
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*
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* Control Register Bit Definition
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*/
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#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
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#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
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#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
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#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
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#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
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#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
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#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
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#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
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#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
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#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
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/* @}*/
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/** @name Mode Register
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*
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* The mode register (MR) defines the mode of transfer as well as the data
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* format. If this register is modified during transmission or reception,
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* data validity cannot be guaranteed.
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*
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* Mode Register Bit Definition
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* @{
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*/
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#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
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#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
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#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
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#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
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#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
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#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
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#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
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#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
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#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
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#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
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#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
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#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
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#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
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#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
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#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
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#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
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#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
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#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
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#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
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#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
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#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
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#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
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#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
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#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
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#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
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/* @} */
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/** @name Interrupt Registers
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*
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* Interrupt control logic uses the interrupt enable register (IER) and the
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* interrupt disable register (IDR) to set the value of the bits in the
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* interrupt mask register (IMR). The IMR determines whether to pass an
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* interrupt to the interrupt status register (ISR).
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* Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
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* interrupt. IMR and ISR are read only, and IER and IDR are write only.
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* Reading either IER or IDR returns 0x00.
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*
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* All four registers have the same bit definitions.
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*
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* @{
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*/
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#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
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#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
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#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
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#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
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#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
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#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
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#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
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#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
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#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
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#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
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#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
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#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
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#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
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#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
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#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
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/* @} */
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/** @name Baud Rate Generator Register
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*
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* The baud rate generator control register (BRGR) is a 16 bit register that
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* controls the receiver bit sample clock and baud rate.
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* Valid values are 1 - 65535.
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*
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* Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
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* in the MR register.
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* @{
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*/
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#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
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#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
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#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
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/** @name Baud Divisor Rate register
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*
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* The baud rate divider register (BDIV) controls how much the bit sample
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* rate is divided by. It sets the baud rate.
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* Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
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*
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* Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
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* the MR_CCLK bit in the MR register.
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* @{
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*/
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#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
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#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
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/* @} */
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/** @name Receiver Timeout Register
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*
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* Use the receiver timeout register (RTR) to detect an idle condition on
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* the receiver data line.
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*
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* @{
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*/
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#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
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#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
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/** @name Receiver FIFO Trigger Level Register
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*
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* Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
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* which the RX FIFO triggers an interrupt event.
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* @{
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*/
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#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
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#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
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#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
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/* @} */
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/** @name Transmit FIFO Trigger Level Register
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*
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* Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
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* which the TX FIFO triggers an interrupt event.
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* @{
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*/
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#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
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#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
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/* @} */
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/** @name Modem Control Register
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*
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* This register (MODEMCR) controls the interface with the modem or data set,
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* or a peripheral device emulating a modem.
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*
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* @{
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*/
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#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
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#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
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#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
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/* @} */
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/** @name Modem Status Register
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*
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* This register (MODEMSR) indicates the current state of the control lines
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* from a modem, or another peripheral device, to the CPU. In addition, four
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* bits of the modem status register provide change information. These bits
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* are set to a logic 1 whenever a control input from the modem changes state.
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*
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* Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
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* status interrupt is generated and this is reflected in the modem status
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* register.
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*
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* @{
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*/
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#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
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#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
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#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
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#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
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#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
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#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
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#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
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#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
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#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
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/* @} */
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/** @name Channel Status Register
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*
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* The channel status register (CSR) is provided to enable the control logic
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* to monitor the status of bits in the channel interrupt status register,
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* even if these are masked out by the interrupt mask register.
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*
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* @{
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*/
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#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
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#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
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#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
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#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
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#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
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#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
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#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
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#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
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#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
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#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
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/* @} */
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/** @name Flow Delay Register
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*
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* Operation of the flow delay register (FLOWDEL) is very similar to the
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* receive FIFO trigger register. An internal trigger signal activates when the
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* FIFO is filled to the level set by this register. This trigger will not
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* cause an interrupt, although it can be read through the channel status
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* register. In hardware flow control mode, RTS is deactivated when the trigger
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* becomes active. RTS only resets when the FIFO level is four less than the
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* level of the flow delay trigger and the flow delay trigger is not activated.
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* A value less than 4 disables the flow delay.
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* @{
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*/
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#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
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/* @} */
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/** @name Receiver FIFO Byte Status Register
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*
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* The Receiver FIFO Status register is used to have a continuous
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* monitoring of the raw unmasked byte status information. The register
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* contains frame, parity and break status information for the top
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* four bytes in the RX FIFO.
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*
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* Receiver FIFO Byte Status Register Bit Definition
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* @{
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*/
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#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
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#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
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#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
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#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
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#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
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#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
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#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
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#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
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#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
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#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
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#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
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#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
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#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
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/* @} */
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/*
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* Defines for backwards compatibility, will be removed
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* in the next version of the driver
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*/
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#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
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#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
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#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
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#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
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#endif /* __ZYNQMP_UART_H__ */
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