250 lines
9.9 KiB
C
250 lines
9.9 KiB
C
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/*
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* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_sysmpu.h"
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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const clock_ip_name_t g_sysmpuClock[FSL_FEATURE_SOC_SYSMPU_COUNT] = SYSMPU_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Codes
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******************************************************************************/
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void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config)
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{
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assert(config);
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uint8_t count;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Un-gate SYSMPU clock */
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CLOCK_EnableClock(g_sysmpuClock[0]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Initializes the regions. */
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for (count = 1; count < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT; count++)
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{
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base->WORD[count][3] = 0; /* VLD/VID+PID. */
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base->WORD[count][0] = 0; /* Start address. */
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base->WORD[count][1] = 0; /* End address. */
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base->WORD[count][2] = 0; /* Access rights. */
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base->RGDAAC[count] = 0; /* Alternate access rights. */
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}
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/* SYSMPU configure. */
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while (config)
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{
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SYSMPU_SetRegionConfig(base, &(config->regionConfig));
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config = config->next;
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}
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/* Enable SYSMPU. */
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SYSMPU_Enable(base, true);
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}
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void SYSMPU_Deinit(SYSMPU_Type *base)
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{
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/* Disable SYSMPU. */
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SYSMPU_Enable(base, false);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate the clock. */
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CLOCK_DisableClock(g_sysmpuClock[0]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform)
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{
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assert(hardwareInform);
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uint32_t cesReg = base->CESR;
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hardwareInform->hardwareRevisionLevel = (cesReg & SYSMPU_CESR_HRL_MASK) >> SYSMPU_CESR_HRL_SHIFT;
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hardwareInform->slavePortsNumbers = (cesReg & SYSMPU_CESR_NSP_MASK) >> SYSMPU_CESR_NSP_SHIFT;
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hardwareInform->regionsNumbers = (sysmpu_region_total_num_t)((cesReg & SYSMPU_CESR_NRGD_MASK) >> SYSMPU_CESR_NRGD_SHIFT);
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}
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void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig)
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{
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assert(regionConfig);
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assert(regionConfig->regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
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uint32_t wordReg = 0;
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uint8_t msPortNum;
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uint8_t regNumber = regionConfig->regionNum;
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/* The start and end address of the region descriptor. */
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base->WORD[regNumber][0] = regionConfig->startAddress;
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base->WORD[regNumber][1] = regionConfig->endAddress;
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/* Set the privilege rights for master 0 ~ master 3. */
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for (msPortNum = 0; msPortNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum++)
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{
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wordReg |= SYSMPU_REGION_RWXRIGHTS_MASTER(
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msPortNum, (((uint32_t)regionConfig->accessRights1[msPortNum].superAccessRights << 3U) |
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(uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights));
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#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
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wordReg |=
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SYSMPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable);
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#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
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}
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#if FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT
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/* Set the normal read write rights for master 4 ~ master 7. */
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for (msPortNum = SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum < FSL_FEATURE_SYSMPU_MASTER_COUNT;
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msPortNum++)
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{
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wordReg |= SYSMPU_REGION_RWRIGHTS_MASTER(msPortNum,
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((uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].readEnable << 1U |
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(uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].writeEnable));
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}
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#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT */
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/* Set region descriptor access rights. */
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base->WORD[regNumber][2] = wordReg;
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wordReg = SYSMPU_WORD_VLD(1);
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#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
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wordReg |= SYSMPU_WORD_PID(regionConfig->processIdentifier) | SYSMPU_WORD_PIDMASK(regionConfig->processIdMask);
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#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
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base->WORD[regNumber][3] = wordReg;
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}
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void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr)
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{
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assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
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base->WORD[regionNum][0] = startAddr;
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base->WORD[regionNum][1] = endAddr;
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}
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void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base,
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uint32_t regionNum,
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uint32_t masterNum,
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const sysmpu_rwxrights_master_access_control_t *accessRights)
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{
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assert(accessRights);
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assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
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assert(masterNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
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uint32_t mask = SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(masterNum);
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uint32_t right = base->RGDAAC[regionNum];
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#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
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mask |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(masterNum);
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#endif
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/* Build rights control value. */
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right &= ~mask;
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right |= SYSMPU_REGION_RWXRIGHTS_MASTER(
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masterNum, ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
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#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
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right |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
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#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
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/* Set low master region access rights. */
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base->RGDAAC[regionNum] = right;
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}
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#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4
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void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base,
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uint32_t regionNum,
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uint32_t masterNum,
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const sysmpu_rwrights_master_access_control_t *accessRights)
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{
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assert(accessRights);
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assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
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assert(masterNum >= SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
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assert(masterNum <= (FSL_FEATURE_SYSMPU_MASTER_COUNT - 1));
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uint32_t mask = SYSMPU_REGION_RWRIGHTS_MASTER_MASK(masterNum);
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uint32_t right = base->RGDAAC[regionNum];
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/* Build rights control value. */
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right &= ~mask;
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right |=
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SYSMPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
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/* Set low master region access rights. */
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base->RGDAAC[regionNum] = right;
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}
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#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */
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bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum)
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{
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uint8_t sperr;
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sperr = ((base->CESR & SYSMPU_CESR_SPERR_MASK) >> SYSMPU_CESR_SPERR_SHIFT) & (0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1));
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return (sperr != 0) ? true : false;
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}
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void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform)
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{
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assert(errInform);
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uint16_t value;
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uint32_t cesReg;
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/* Error address. */
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errInform->address = base->SP[slaveNum].EAR;
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/* Error detail information. */
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value = (base->SP[slaveNum].EDR & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT;
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if (!value)
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{
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errInform->accessControl = kSYSMPU_NoRegionHit;
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}
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else if (!(value & (uint16_t)(value - 1)))
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{
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errInform->accessControl = kSYSMPU_NoneOverlappRegion;
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}
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else
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{
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errInform->accessControl = kSYSMPU_OverlappRegion;
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}
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value = base->SP[slaveNum].EDR;
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errInform->master = (uint32_t)((value & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT);
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errInform->attributes = (sysmpu_err_attributes_t)((value & SYSMPU_EDR_EATTR_MASK) >> SYSMPU_EDR_EATTR_SHIFT);
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errInform->accessType = (sysmpu_err_access_type_t)((value & SYSMPU_EDR_ERW_MASK) >> SYSMPU_EDR_ERW_SHIFT);
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#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
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errInform->processorIdentification = (uint8_t)((value & SYSMPU_EDR_EPID_MASK) >> SYSMPU_EDR_EPID_SHIFT);
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#endif
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/* Clears error slave port bit. */
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cesReg = (base->CESR & ~SYSMPU_CESR_SPERR_MASK) | ((0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)) << SYSMPU_CESR_SPERR_SHIFT);
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base->CESR = cesReg;
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}
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