2015-09-04 12:30:20 +08:00
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/*
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2015-09-04 21:58:08 +08:00
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* File : dm365_timer.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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2015-09-04 12:30:20 +08:00
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*
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2015-09-04 21:58:08 +08:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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2015-09-04 12:30:20 +08:00
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*
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2015-09-04 21:58:08 +08:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2010-11-13 weety first version
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2015-09-04 12:30:20 +08:00
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*/
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2015-09-04 21:58:08 +08:00
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2015-09-04 12:30:20 +08:00
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#ifndef __ASM_ARCH_TIME_H
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#define __ASM_ARCH_TIME_H
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/* Timer register offsets */
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#define PID12 0x0
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#define TIM12 0x10
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#define TIM34 0x14
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#define PRD12 0x18
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#define PRD34 0x1c
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#define TCR 0x20
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#define TGCR 0x24
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#define WDTCR 0x28
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#define CMP12(n) (0x60 + ((n) << 2))
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/* Timer register bitfields */
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#define ENAMODE12_SHIFT 6
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#define ENAMODE34_SHIFT 22
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#define TCR_ENAMODE_DISABLE 0x0
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#define TCR_ENAMODE_ONESHOT 0x1
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#define TCR_ENAMODE_PERIODIC 0x2
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#define TCR_ENAMODE_MASK 0x3
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#define TGCR_TIMMODE_SHIFT 2
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#define TGCR_TIMMODE_64BIT_GP 0x0
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#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
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#define TGCR_TIMMODE_64BIT_WDOG 0x2
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#define TGCR_TIMMODE_32BIT_CHAINED 0x3
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#define TGCR_TIM12RS_SHIFT 0
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#define TGCR_TIM34RS_SHIFT 1
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#define TGCR_RESET 0x0
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#define TGCR_UNRESET 0x1
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#define TGCR_RESET_MASK 0x3
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#define WDTCR_WDEN_SHIFT 14
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#define WDTCR_WDEN_DISABLE 0x0
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#define WDTCR_WDEN_ENABLE 0x1
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#define WDTCR_WDKEY_SHIFT 16
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#define WDTCR_WDKEY_SEQ0 0xA5C6
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#define WDTCR_WDKEY_SEQ1 0xDA7E
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enum {
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T0_BOT,
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T0_TOP,
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T1_BOT,
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T1_TOP,
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NUM_TIMERS
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};
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#endif /* __ASM_ARCH_TIME_H__ */
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