377 lines
16 KiB
C
377 lines
16 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_flash.h
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//
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// TITLE: FLASH Register Definitions.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef __F2837xD_FLASH_H__
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#define __F2837xD_FLASH_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// FLASH Individual Register Bit Definitions:
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struct FRDCNTL_BITS { // bits description
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Uint16 rsvd1:8; // 7:0 Reserved
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Uint16 RWAIT:4; // 11:8 Random Read Waitstate
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Uint16 rsvd2:4; // 15:12 Reserved
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Uint16 rsvd3:16; // 31:16 Reserved
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};
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union FRDCNTL_REG {
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Uint32 all;
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struct FRDCNTL_BITS bit;
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};
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struct FBAC_BITS { // bits description
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Uint16 VREADST:8; // 7:0 VREAD Setup Time Count
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Uint16 rsvd1:8; // 15:8 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union FBAC_REG {
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Uint32 all;
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struct FBAC_BITS bit;
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};
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struct FBFALLBACK_BITS { // bits description
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Uint16 BNKPWR0:2; // 1:0 Bank Power Mode
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Uint16 rsvd1:14; // 15:2 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union FBFALLBACK_REG {
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Uint32 all;
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struct FBFALLBACK_BITS bit;
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};
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struct FBPRDY_BITS { // bits description
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Uint16 BANKRDY:1; // 0 Flash Bank Active Power State
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Uint16 rsvd1:14; // 14:1 Reserved
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Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union FBPRDY_REG {
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Uint32 all;
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struct FBPRDY_BITS bit;
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};
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struct FPAC1_BITS { // bits description
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Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode
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Uint16 rsvd1:15; // 15:1 Reserved
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Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count
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Uint16 rsvd2:4; // 31:28 Reserved
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};
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union FPAC1_REG {
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Uint32 all;
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struct FPAC1_BITS bit;
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};
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struct FMSTAT_BITS { // bits description
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Uint16 rsvd1:1; // 0 Reserved
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Uint16 rsvd2:1; // 1 Reserved
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Uint16 rsvd3:1; // 2 Reserved
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Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status
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Uint16 CSTAT:1; // 4 Command Fail Status
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Uint16 INVDAT:1; // 5 Invalid Data
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Uint16 PGM:1; // 6 Program Operation Status
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Uint16 ERS:1; // 7 Erase Operation Status
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Uint16 BUSY:1; // 8 Busy Bit
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Uint16 rsvd4:1; // 9 Reserved
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Uint16 EV:1; // 10 Erase Verify Status
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Uint16 rsvd5:1; // 11 Reserved
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Uint16 PGV:1; // 12 Programming Verify Status
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Uint16 rsvd6:1; // 13 Reserved
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Uint16 rsvd7:1; // 14 Reserved
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Uint16 rsvd8:1; // 15 Reserved
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Uint16 rsvd9:1; // 16 Reserved
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Uint16 rsvd10:1; // 17 Reserved
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Uint16 rsvd11:14; // 31:18 Reserved
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};
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union FMSTAT_REG {
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Uint32 all;
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struct FMSTAT_BITS bit;
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};
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struct FRD_INTF_CTRL_BITS { // bits description
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Uint16 PREFETCH_EN:1; // 0 Prefetch Enable
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Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable
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Uint16 rsvd1:14; // 15:2 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union FRD_INTF_CTRL_REG {
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Uint32 all;
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struct FRD_INTF_CTRL_BITS bit;
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};
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struct FLASH_CTRL_REGS {
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union FRDCNTL_REG FRDCNTL; // Flash Read Control Register
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Uint16 rsvd1[28]; // Reserved
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union FBAC_REG FBAC; // Flash Bank Access Control Register
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union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register
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union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register
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union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1
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Uint16 rsvd2[4]; // Reserved
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union FMSTAT_REG FMSTAT; // Flash Module Status Register
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Uint16 rsvd3[340]; // Reserved
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union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register
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};
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struct ECC_ENABLE_BITS { // bits description
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Uint16 ENABLE:4; // 3:0 Enable ECC
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Uint16 rsvd1:12; // 15:4 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union ECC_ENABLE_REG {
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Uint32 all;
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struct ECC_ENABLE_BITS bit;
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};
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struct ERR_STATUS_BITS { // bits description
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Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0
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Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1
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Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred
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Uint16 rsvd1:13; // 15:3 Reserved
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Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0
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Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1
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Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred
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Uint16 rsvd2:13; // 31:19 Reserved
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};
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union ERR_STATUS_REG {
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Uint32 all;
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struct ERR_STATUS_BITS bit;
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};
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struct ERR_POS_BITS { // bits description
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Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits
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Uint16 rsvd1:2; // 7:6 Reserved
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Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits
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Uint16 rsvd2:7; // 15:9 Reserved
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Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits
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Uint16 rsvd3:2; // 23:22 Reserved
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Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits
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Uint16 rsvd4:7; // 31:25 Reserved
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};
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union ERR_POS_REG {
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Uint32 all;
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struct ERR_POS_BITS bit;
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};
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struct ERR_STATUS_CLR_BITS { // bits description
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Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear
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Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear
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Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear
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Uint16 rsvd1:13; // 15:3 Reserved
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Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear
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Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear
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Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear
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Uint16 rsvd2:13; // 31:19 Reserved
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};
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union ERR_STATUS_CLR_REG {
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Uint32 all;
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struct ERR_STATUS_CLR_BITS bit;
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};
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struct ERR_CNT_BITS { // bits description
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Uint16 ERR_CNT:16; // 15:0 Error counter
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Uint16 rsvd1:16; // 31:16 Reserved
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};
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union ERR_CNT_REG {
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Uint32 all;
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struct ERR_CNT_BITS bit;
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};
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struct ERR_THRESHOLD_BITS { // bits description
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Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold
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Uint16 rsvd1:16; // 31:16 Reserved
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};
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union ERR_THRESHOLD_REG {
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Uint32 all;
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struct ERR_THRESHOLD_BITS bit;
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};
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struct ERR_INTFLG_BITS { // bits description
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Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag
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Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag
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Uint16 rsvd1:14; // 15:2 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union ERR_INTFLG_REG {
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Uint32 all;
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struct ERR_INTFLG_BITS bit;
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};
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struct ERR_INTCLR_BITS { // bits description
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Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear
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Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear
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Uint16 rsvd1:14; // 15:2 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union ERR_INTCLR_REG {
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Uint32 all;
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struct ERR_INTCLR_BITS bit;
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};
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struct FADDR_TEST_BITS { // bits description
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Uint16 rsvd1:3; // 2:0 Reserved
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Uint16 ADDRL:13; // 15:3 ECC Address Low
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Uint16 ADDRH:6; // 21:16 ECC Address High
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Uint16 rsvd2:10; // 31:22 Reserved
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};
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union FADDR_TEST_REG {
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Uint32 all;
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struct FADDR_TEST_BITS bit;
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};
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struct FECC_TEST_BITS { // bits description
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Uint16 ECC:8; // 7:0 ECC Control Bits
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Uint16 rsvd1:8; // 15:8 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union FECC_TEST_REG {
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Uint32 all;
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struct FECC_TEST_BITS bit;
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};
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struct FECC_CTRL_BITS { // bits description
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Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic
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Uint16 ECC_SELECT:1; // 1 ECC Bit Select
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Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation
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Uint16 rsvd1:13; // 15:3 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union FECC_CTRL_REG {
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Uint32 all;
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struct FECC_CTRL_BITS bit;
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};
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struct FECC_STATUS_BITS { // bits description
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Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error
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Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error
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Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error
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Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error
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Uint16 rsvd1:7; // 15:9 Reserved
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Uint16 rsvd2:16; // 31:16 Reserved
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};
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union FECC_STATUS_REG {
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Uint32 all;
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struct FECC_STATUS_BITS bit;
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};
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struct FLASH_ECC_REGS {
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union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable
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Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low
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Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High
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Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low
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Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High
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union ERR_STATUS_REG ERR_STATUS; // Error Status
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union ERR_POS_REG ERR_POS; // Error Position
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union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear
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union ERR_CNT_REG ERR_CNT; // Error Control
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union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold
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union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag
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union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear
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Uint32 FDATAH_TEST; // Data High Test
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Uint32 FDATAL_TEST; // Data Low Test
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union FADDR_TEST_REG FADDR_TEST; // ECC Test Address
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union FECC_TEST_REG FECC_TEST; // ECC Test Address
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union FECC_CTRL_REG FECC_CTRL; // ECC Control
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Uint32 FOUTH_TEST; // Test Data Out High
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Uint32 FOUTL_TEST; // Test Data Out Low
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union FECC_STATUS_REG FECC_STATUS; // ECC Status
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};
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struct PUMPREQUEST_BITS { // bits description
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Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2
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Uint16 rsvd1:14; // 15:2 Reserved
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Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register
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};
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union PUMPREQUEST_REG {
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Uint32 all;
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struct PUMPREQUEST_BITS bit;
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};
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struct FLASH_PUMP_SEMAPHORE_REGS {
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union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register
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};
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//---------------------------------------------------------------------------
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// FLASH External References & Function Declarations:
|
||
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|
//
|
||
|
|
#ifdef CPU1
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||
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|
extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
|
||
|
|
extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
|
||
|
|
extern volatile struct FLASH_ECC_REGS Flash0EccRegs;
|
||
|
|
#endif
|
||
|
|
#ifdef CPU2
|
||
|
|
extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
|
||
|
|
extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
|
||
|
|
extern volatile struct FLASH_ECC_REGS Flash0EccRegs;
|
||
|
|
#endif
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif /* extern "C" */
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//===========================================================================
|
||
|
|
// End of file.
|
||
|
|
//===========================================================================
|