344 lines
9.8 KiB
C
344 lines
9.8 KiB
C
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/*
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* @brief LPC8xx Multi-Rate Timer (MRT) registers and driver functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __MRT_8XX_H_
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#define __MRT_8XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup MRT_8XX CHIP: LPC8xx Multi-Rate Timer driver
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* @ingroup CHIP_8XX_Drivers
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* @{
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*/
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/**
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* @brief LPC8xx MRT chip configuration
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*/
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#define MRT_CHANNELS_NUM (4)
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#define MRT_NO_IDLE_CHANNEL (0x40)
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/**
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* @brief MRT register block structure
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*/
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typedef struct {
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__IO uint32_t INTVAL; /*!< Timer interval register */
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__O uint32_t TIMER; /*!< Timer register */
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__IO uint32_t CTRL; /*!< Timer control register */
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__IO uint32_t STAT; /*!< Timer status register */
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} LPC_MRT_CH_T;
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/**
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* @brief MRT register block structure
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*/
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typedef struct {
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LPC_MRT_CH_T CHANNEL[MRT_CHANNELS_NUM];
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uint32_t unused[45];
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__O uint32_t IDLE_CH;
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__IO uint32_t IRQ_FLAG;
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} LPC_MRT_T;
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/* Reserved bits masks for registers */
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#define MRT_CTRL_RESERVED (~7)
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#define MRT_STAT_RESERVED (~3)
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/**
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* @brief MRT Interrupt Modes enum
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*/
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typedef enum MRT_MODE {
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MRT_MODE_REPEAT = (0 << 1), /*!< MRT Repeat interrupt mode */
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MRT_MODE_ONESHOT = (1 << 1) /*!< MRT One-shot interrupt mode */
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} MRT_MODE_T;
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/**
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* @brief MRT register bit fields & masks
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*/
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/* MRT Time interval register bit fields */
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#define MRT_INTVAL_IVALUE (0x7FFFFFFFUL) /* Maximum interval load value and mask */
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#define MRT_INTVAL_LOAD (0x80000000UL) /* Force immediate load of timer interval register bit */
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/* MRT Control register bit fields & masks */
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#define MRT_CTRL_INTEN_MASK (0x01)
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#define MRT_CTRL_MODE_MASK (0x06)
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/* MRT Status register bit fields & masks */
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#define MRT_STAT_INTFLAG (0x01)
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#define MRT_STAT_RUNNING (0x02)
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/* Pointer to individual MR register blocks */
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#define LPC_MRT_CH0 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[0])
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#define LPC_MRT_CH1 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[1])
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#define LPC_MRT_CH2 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[2])
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#define LPC_MRT_CH3 ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[3])
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#define LPC_MRT_CH(ch) ((LPC_MRT_CH_T *) &LPC_MRT->CHANNEL[(ch)])
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/* Global interrupt flag register interrupt mask/clear values */
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#define MRT0_INTFLAG (1)
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#define MRT1_INTFLAG (2)
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#define MRT2_INTFLAG (4)
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#define MRT3_INTFLAG (8)
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#define MRTn_INTFLAG(ch) (1 << (ch))
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/**
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* @brief Initializes the MRT
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* @return Nothing
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*/
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STATIC INLINE void Chip_MRT_Init(void)
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{
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/* Enable the clock to the register interface */
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_MRT);
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/* Reset MRT */
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Chip_SYSCTL_PeriphReset(RESET_MRT);
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}
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/**
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* @brief De-initializes the MRT Channel
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* @return Nothing
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*/
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STATIC INLINE void Chip_MRT_DeInit(void)
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{
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/* Disable the clock to the MRT */
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Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_MRT);
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}
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/**
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* @brief Returns a pointer to the register block for a MRT channel
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* @param ch : MRT channel tog et register block for (0..3)
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* @return Pointer to the MRT register block for the channel
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*/
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STATIC INLINE LPC_MRT_CH_T *Chip_MRT_GetRegPtr(uint8_t ch)
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{
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return LPC_MRT_CH(ch);
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}
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/**
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* @brief Returns the timer time interval value
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* @param pMRT : Pointer to selected MRT Channel
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* @return Timer time interval value (IVALUE)
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*/
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STATIC INLINE uint32_t Chip_MRT_GetInterval(LPC_MRT_CH_T *pMRT)
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{
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return pMRT->INTVAL;
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}
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/**
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* @brief Sets the timer time interval value
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* @param pMRT : Pointer to selected MRT Channel
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* @param interval : The interval timeout (31-bits)
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* @return Nothing
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* @note Setting bit 31 in timer time interval register causes the time interval value
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* to load immediately, otherwise the time interval value will be loaded in
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* next timer cycle.<br>
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* Example: Chip_MRT_SetInterval(pMRT, 0x500 | MRT_INTVAL_LOAD); // Will load timer interval immediately<br>
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* Example: Chip_MRT_SetInterval(pMRT, 0x500); // Will load timer interval after internal expires
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*/
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STATIC INLINE void Chip_MRT_SetInterval(LPC_MRT_CH_T *pMRT, uint32_t interval)
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{
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pMRT->INTVAL = interval;
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}
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/**
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* @brief Returns the current timer value
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* @param pMRT : Pointer to selected MRT Channel
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* @return The current timer value
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*/
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STATIC INLINE uint32_t Chip_MRT_GetTimer(LPC_MRT_CH_T *pMRT)
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{
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return pMRT->TIMER;
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}
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/**
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* @brief Returns true if the timer is enabled
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* @param pMRT : Pointer to selected MRT Channel
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* @return True if enabled, Flase if not enabled
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*/
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STATIC INLINE bool Chip_MRT_GetEnabled(LPC_MRT_CH_T *pMRT)
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{
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return (bool) ((pMRT->CTRL & MRT_CTRL_INTEN_MASK) != 0);
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}
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/**
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* @brief Enables the timer
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* @param pMRT : Pointer to selected MRT Channel
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* @return Nothing
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*/
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STATIC INLINE void Chip_MRT_SetEnabled(LPC_MRT_CH_T *pMRT)
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{
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pMRT->CTRL = MRT_CTRL_INTEN_MASK | (pMRT->CTRL & ~MRT_CTRL_RESERVED);
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}
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/**
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* @brief Disables the timer
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* @param pMRT : Pointer to selected MRT Channel
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* @return Nothing
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*/
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STATIC INLINE void Chip_MRT_SetDisabled(LPC_MRT_CH_T *pMRT)
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{
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pMRT->CTRL &= ~(MRT_CTRL_INTEN_MASK | MRT_CTRL_RESERVED);
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}
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/**
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* @brief Returns the timer mode (repeat or one-shot)
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* @param pMRT : Pointer to selected MRT Channel
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* @return The current timer mode
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*/
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STATIC INLINE MRT_MODE_T Chip_MRT_GetMode(LPC_MRT_CH_T *pMRT)
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{
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return (MRT_MODE_T) (pMRT->CTRL & MRT_CTRL_MODE_MASK);
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}
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/**
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* @brief Sets the timer mode (repeat or one-shot)
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* @param pMRT : Pointer to selected MRT Channel
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* @param mode : Timer mode
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* @return Nothing
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*/
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STATIC INLINE void Chip_MRT_SetMode(LPC_MRT_CH_T *pMRT, MRT_MODE_T mode)
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{
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uint32_t reg;
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reg = pMRT->CTRL & ~(MRT_CTRL_MODE_MASK | MRT_CTRL_RESERVED);
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pMRT->CTRL = reg | (uint32_t) mode;
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}
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/**
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* @brief Check if the timer is configured in repeat mode
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* @param pMRT : Pointer to selected MRT Channel
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* @return True if in repeat mode, False if in one-shot mode
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*/
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STATIC INLINE bool Chip_MRT_IsRepeatMode(LPC_MRT_CH_T *pMRT)
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{
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return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? false : true;
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}
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/**
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* @brief Check if the timer is configured in one-shot mode
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* @param pMRT : Pointer to selected MRT Channel
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* @return True if in one-shot mode, False if in repeat mode
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*/
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STATIC INLINE bool Chip_MRT_IsOneShotMode(LPC_MRT_CH_T *pMRT)
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{
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return ((pMRT->CTRL & MRT_CTRL_MODE_MASK) != 0) ? true : false;
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}
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/**
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* @brief Check if the timer has an interrupt pending
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* @param pMRT : Pointer to selected MRT Channel
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* @return True if interrupt is pending, False if no interrupt is pending
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*/
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STATIC INLINE bool Chip_MRT_IntPending(LPC_MRT_CH_T *pMRT)
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{
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return (bool) ((pMRT->STAT & MRT_STAT_INTFLAG) != 0);
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}
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/**
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* @brief Clears the pending interrupt (if any)
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* @param pMRT : Pointer to selected MRT Channel
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* @return Nothing
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*/
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STATIC INLINE void Chip_MRT_IntClear(LPC_MRT_CH_T *pMRT)
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{
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pMRT->STAT = MRT_STAT_INTFLAG | (pMRT->STAT & ~MRT_STAT_RESERVED);
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}
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/**
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* @brief Check if the timer is running
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* @param pMRT : Pointer to selected MRT Channel
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* @return True if running, False if stopped
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*/
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STATIC INLINE bool Chip_MRT_Running(LPC_MRT_CH_T *pMRT)
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{
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return (bool) ((pMRT->STAT & MRT_STAT_RUNNING) != 0);
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}
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/**
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* @brief Returns the IDLE channel value
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* @return IDLE channel value (unshifted in bits 7..4)
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*/
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STATIC INLINE uint8_t Chip_MRT_GetIdleChannel(void)
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{
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return (uint8_t) (LPC_MRT->IDLE_CH);
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}
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/**
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* @brief Returns the IDLE channel value
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* @return IDLE channel value (shifted in bits 3..0)
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*/
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STATIC INLINE uint8_t Chip_MRT_GetIdleChannelShifted(void)
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{
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return (uint8_t) (Chip_MRT_GetIdleChannel() >> 4);
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}
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/**
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* @brief Returns the interrupt pending status for all MRT channels
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* @return IRQ pending channel bitfield(bit 0 = MRT0, bit 1 = MRT1, etc.)
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*/
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STATIC INLINE uint32_t Chip_MRT_GetIntPending(void)
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{
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return LPC_MRT->IRQ_FLAG;
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}
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/**
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* @brief Returns the interrupt pending status for a singel MRT channel
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* @param ch : Channel to check pending interrupt status for
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* @return IRQ pending channel number
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*/
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STATIC INLINE bool Chip_MRT_GetIntPendingByChannel(uint8_t ch)
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{
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return (bool) (((LPC_MRT->IRQ_FLAG >> ch) & 1) != 0);
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}
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/**
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* @brief Clears the interrupt pending status for one or more MRT channels
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* @param mask : Channels to clear (bit 0 = MRT0, bit 1 = MRT1, etc.)
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* @return Nothing
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* @note Use this function to clear multiple interrupt pending states in
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* a single call via the IRQ_FLAG register. Performs the same function for
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* all MRT channels in a single call as the Chip_MRT_IntClear() does for a
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* single channel.
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*/
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STATIC INLINE void Chip_MRT_ClearIntPending(uint32_t mask)
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{
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LPC_MRT->IRQ_FLAG = mask;
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MRT_8XX_H_ */
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