103 lines
4.7 KiB
Plaintext
103 lines
4.7 KiB
Plaintext
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/***************************************************************************//**
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* \file HC32F448.icf
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* \version 1.0
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*
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* \brief Linker file for the IAR compiler.
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*
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********************************************************************************
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* \copyright
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by XHSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*******************************************************************************/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
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// Check that necessary symbols have been passed to linker via command line interface
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if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
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error "Link location not defined or not supported!";
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}
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if((!isdefinedsymbol(_HC32F448_256K_)) && (!isdefinedsymbol(_HC32F448_128K_))) {
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error "Mcu type or size not defined or not supported!";
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}
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/*******************************************************************************
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* Memory address and size definitions
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******************************************************************************/
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define symbol ram1_base_address = 0x1FFF8000;
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define symbol ram1_end_address = 0x20007FFF;
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if(isdefinedsymbol(_LINK_RAM_)) {
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define symbol ram_start_reserve = 0x8000;
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define symbol rom1_base_address = ram1_base_address;
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define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
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define symbol rom2_base_address = 0x0;
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define symbol rom2_end_address = 0x0;
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} else {
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define symbol ram_start_reserve = 0x0;
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define symbol rom1_base_address = 0x0;
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define symbol rom2_base_address = 0x03000C00;
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define symbol rom2_end_address = 0x03000FFF;
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if(isdefinedsymbol(_HC32F448_256K_)) {
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define symbol rom1_end_address = 0x0003FFFF;
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} else if (isdefinedsymbol(_HC32F448_128K_)) {
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define symbol rom1_end_address = 0x0001FFFF;
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}
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}
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
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define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
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define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
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define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
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define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
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define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
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define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
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define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
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define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
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define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
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define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
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define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
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define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
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define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
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define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
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define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
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define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
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define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
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define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
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define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0xC00;
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define symbol __ICFEDIT_size_proc_stack__ = 0x0;
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define symbol __ICFEDIT_size_heap__ = 0x400;
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/**** End of ICF editor section. ###ICF###*/
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/*******************************************************************************
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* Memory definitions
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******************************************************************************/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
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define region OTP_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
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| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in OTP_region { readonly section .otp_data };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };
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