254 lines
8.1 KiB
INI
254 lines
8.1 KiB
INI
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# Copyright 2021 hpmicro
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# SPDX-License-Identifier: BSD-3-Clause
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flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000
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proc init_clock {} {
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$::_TARGET0 riscv dmi_write 0x39 0xF4002000
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$::_TARGET0 riscv dmi_write 0x3C 0x1
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$::_TARGET0 riscv dmi_write 0x39 0xF4002000
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$::_TARGET0 riscv dmi_write 0x3C 0x2
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$::_TARGET0 riscv dmi_write 0x39 0xF4000800
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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$::_TARGET0 riscv dmi_write 0x39 0xF4000810
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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$::_TARGET0 riscv dmi_write 0x39 0xF4000820
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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$::_TARGET0 riscv dmi_write 0x39 0xF4000830
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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echo "clocks has been enabled!"
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}
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proc init_sdram { } {
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# configure dram frequency
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# 133Mhz pll1_clk0: 266Mhz divide by 2
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#$::_TARGET0 riscv dmi_write 0x39 0xF4001820
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$::_TARGET0 riscv dmi_write 0x3C 0x201
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# 166Mhz pll2_clk0: 333Mhz divide by 2
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$::_TARGET0 riscv dmi_write 0x39 0xF4001820
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$::_TARGET0 riscv dmi_write 0x3C 0x401
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# PD13
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$::_TARGET0 riscv dmi_write 0x39 0xF4040368
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD12
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$::_TARGET0 riscv dmi_write 0x39 0xF4040360
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD10
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$::_TARGET0 riscv dmi_write 0x39 0xF4040350
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD09
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$::_TARGET0 riscv dmi_write 0x39 0xF4040348
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD08
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$::_TARGET0 riscv dmi_write 0x39 0xF4040340
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD07
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$::_TARGET0 riscv dmi_write 0x39 0xF4040338
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD06
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$::_TARGET0 riscv dmi_write 0x39 0xF4040330
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD05
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$::_TARGET0 riscv dmi_write 0x39 0xF4040328
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD04
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$::_TARGET0 riscv dmi_write 0x39 0xF4040320
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD03
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$::_TARGET0 riscv dmi_write 0x39 0xF4040318
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD02
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$::_TARGET0 riscv dmi_write 0x39 0xF4040310
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD01
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$::_TARGET0 riscv dmi_write 0x39 0xF4040308
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PD00
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$::_TARGET0 riscv dmi_write 0x39 0xF4040300
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC29
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$::_TARGET0 riscv dmi_write 0x39 0xF40402E8
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC28
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$::_TARGET0 riscv dmi_write 0x39 0xF40402E0
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC27
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$::_TARGET0 riscv dmi_write 0x39 0xF40402D8
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC22
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$::_TARGET0 riscv dmi_write 0x39 0xF40402B0
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC21
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$::_TARGET0 riscv dmi_write 0x39 0xF40402A8
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC17
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$::_TARGET0 riscv dmi_write 0x39 0xF4040288
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC15
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$::_TARGET0 riscv dmi_write 0x39 0xF4040278
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC12
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$::_TARGET0 riscv dmi_write 0x39 0xF4040260
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC11
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$::_TARGET0 riscv dmi_write 0x39 0xF4040258
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC10
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$::_TARGET0 riscv dmi_write 0x39 0xF4040250
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC09
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$::_TARGET0 riscv dmi_write 0x39 0xF4040248
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC08
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$::_TARGET0 riscv dmi_write 0x39 0xF4040240
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC07
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$::_TARGET0 riscv dmi_write 0x39 0xF4040238
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC06
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$::_TARGET0 riscv dmi_write 0x39 0xF4040230
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC05
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$::_TARGET0 riscv dmi_write 0x39 0xF4040228
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC04
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$::_TARGET0 riscv dmi_write 0x39 0xF4040220
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC14
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$::_TARGET0 riscv dmi_write 0x39 0xF4040270
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC13
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$::_TARGET0 riscv dmi_write 0x39 0xF4040268
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC16
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# $::_TARGET0 riscv dmi_write 0x39 0xF4040280
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$::_TARGET0 riscv dmi_write 0x3C 0x1000C
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# PC26
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$::_TARGET0 riscv dmi_write 0x39 0xF40402D0
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC25
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$::_TARGET0 riscv dmi_write 0x39 0xF40402C8
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC19
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$::_TARGET0 riscv dmi_write 0x39 0xF4040298
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC18
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$::_TARGET0 riscv dmi_write 0x39 0xF4040290
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC23
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$::_TARGET0 riscv dmi_write 0x39 0xF40402B8
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC24
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$::_TARGET0 riscv dmi_write 0x39 0xF40402C0
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC30
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$::_TARGET0 riscv dmi_write 0x39 0xF40402F0
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC31
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$::_TARGET0 riscv dmi_write 0x39 0xF40402F8
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC02
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$::_TARGET0 riscv dmi_write 0x39 0xF4040210
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# PC03
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$::_TARGET0 riscv dmi_write 0x39 0xF4040218
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$::_TARGET0 riscv dmi_write 0x3C 0xC
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# dramc configuration
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$::_TARGET0 riscv dmi_write 0x39 0xF3050000
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$::_TARGET0 riscv dmi_write 0x3C 0x1
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sleep 10
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$::_TARGET0 riscv dmi_write 0x39 0xF3050000
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$::_TARGET0 riscv dmi_write 0x3C 0x2
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$::_TARGET0 riscv dmi_write 0x39 0xF3050008
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$::_TARGET0 riscv dmi_write 0x3C 0x30524
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$::_TARGET0 riscv dmi_write 0x39 0xF305000C
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$::_TARGET0 riscv dmi_write 0x3C 0x6030524
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$::_TARGET0 riscv dmi_write 0x39 0xF3050000
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$::_TARGET0 riscv dmi_write 0x3C 0x10000000
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# 32MB
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$::_TARGET0 riscv dmi_write 0x39 0xF3050010
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$::_TARGET0 riscv dmi_write 0x3C 0x4000001b
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$::_TARGET0 riscv dmi_write 0x39 0xF3050014
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$::_TARGET0 riscv dmi_write 0x3C 0
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# 16-bit
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$::_TARGET0 riscv dmi_write 0x39 0xF3050040
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$::_TARGET0 riscv dmi_write 0x3C 0xf31
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# 133Mhz configuration
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#$::_TARGET0 riscv dmi_write 0x39 0xF3050044
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$::_TARGET0 riscv dmi_write 0x3C 0x884e22
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# 166Mhz configuration
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$::_TARGET0 riscv dmi_write 0x39 0xF3050044
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$::_TARGET0 riscv dmi_write 0x3C 0x884e33
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$::_TARGET0 riscv dmi_write 0x39 0xF3050048
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$::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
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$::_TARGET0 riscv dmi_write 0x39 0xF3050048
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$::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
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$::_TARGET0 riscv dmi_write 0x39 0xF305004C
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$::_TARGET0 riscv dmi_write 0x3C 0x2020300
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# config delay cell
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$::_TARGET0 riscv dmi_write 0x39 0xF3050150
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$::_TARGET0 riscv dmi_write 0x3C 0x3b
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$::_TARGET0 riscv dmi_write 0x39 0xF3050150
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$::_TARGET0 riscv dmi_write 0x3C 0x203b
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$::_TARGET0 riscv dmi_write 0x39 0xF3050094
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF3050098
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$::_TARGET0 riscv dmi_write 0x3C 0
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# precharge all
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$::_TARGET0 riscv dmi_write 0x39 0xF3050090
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$::_TARGET0 riscv dmi_write 0x3C 0x40000000
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$::_TARGET0 riscv dmi_write 0x39 0xF305009C
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$::_TARGET0 riscv dmi_write 0x3C 0xA55A000F
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sleep 500
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$::_TARGET0 riscv dmi_write 0x39 0xF305003C
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$::_TARGET0 riscv dmi_write 0x3C 0x3
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# auto refresh
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$::_TARGET0 riscv dmi_write 0x39 0xF305009C
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$::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
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sleep 500
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$::_TARGET0 riscv dmi_write 0x39 0xF305003C
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$::_TARGET0 riscv dmi_write 0x3C 0x3
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$::_TARGET0 riscv dmi_write 0x39 0xF305009C
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$::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
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sleep 500
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$::_TARGET0 riscv dmi_write 0x39 0xF305003C
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$::_TARGET0 riscv dmi_write 0x3C 0x3
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# set mode
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$::_TARGET0 riscv dmi_write 0x39 0xF30500A0
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$::_TARGET0 riscv dmi_write 0x3C 0x33
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$::_TARGET0 riscv dmi_write 0x39 0xF305009C
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$::_TARGET0 riscv dmi_write 0x3C 0xA55A000A
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sleep 500
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$::_TARGET0 riscv dmi_write 0x39 0xF305003C
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$::_TARGET0 riscv dmi_write 0x3C 0x3
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$::_TARGET0 riscv dmi_write 0x39 0xF305004C
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$::_TARGET0 riscv dmi_write 0x3C 0x2020301
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echo "SDRAM has been initialized"
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}
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$_TARGET0 configure -event reset-init {
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init_clock
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init_sdram
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}
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$_TARGET0 configure -event gdb-attach {
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reset halt
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}
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