495 lines
14 KiB
C
495 lines
14 KiB
C
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/* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY¡¯S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS¡¯SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY¡¯S TECHNOLOGY.
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hal_interrupt.h>
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#include <hal_clk.h>
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#include <sunxi_hal_gpadc.h>
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#include <hal_reset.h>
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hal_gpadc_t hal_gpadc;
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#if defined(CONFIG_SOC_SUN20IW1)
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static hal_gpadc_status_t hal_gpadc_clk_init(hal_gpadc_t *gpadc)
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{
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hal_clk_type_t clk_type = HAL_SUNXI_CCU;
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hal_clk_id_t gpadc_clk_id = gpadc->bus_clk;
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hal_clk_t mclk;
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hal_reset_type_t reset_type = HAL_SUNXI_RESET;
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hal_reset_id_t gpadc_reset_id = gpadc->rst_clk;
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struct reset_control *reset;
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mclk = hal_clock_get(clk_type, gpadc_clk_id);
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if(hal_clock_enable(mclk))
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{
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GPADC_ERR("gpadc clk enable failed!\n");
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return GPADC_ERROR;
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}
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gpadc->mbus_clk = mclk;
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reset = hal_reset_control_get(reset_type, gpadc_reset_id);
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if (hal_reset_control_deassert(reset))
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{
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GPADC_ERR("gpadc reset deassert failed!\n");
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return GPADC_ERROR;
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}
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hal_reset_control_put(reset);
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return GPADC_OK;
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}
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#else
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static hal_gpadc_status_t hal_gpadc_clk_init(hal_gpadc_t *gpadc)
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{
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#if !defined(CONFIG_ARCH_SUN8IW18P1)
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if (hal_clk_set_parent(gpadc->mclk, gpadc->pclk))
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{
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GPADC_ERR("[gpadc] clk set parent failed!");
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return GPADC_ERROR;
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}
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#endif
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if (hal_clock_enable(gpadc->mclk))
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{
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GPADC_ERR("[gpadc] clk enable mclk failed!");
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return GPADC_ERROR;
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}
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return GPADC_OK;
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}
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#endif
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static int gpadc_channel_check_valid(hal_gpadc_channel_t channal)
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{
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hal_gpadc_t *gpadc = &hal_gpadc;
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return channal < gpadc->channel_num ? 0 : -1 ;
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}
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static void gpadc_channel_select(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_CS_EN_REG);
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reg_val |= (0x01 << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_CS_EN_REG);
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}
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static void gpadc_channel_deselect(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_CS_EN_REG);
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reg_val &= ~(0x01 << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_CS_EN_REG);
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}
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static void gpadc_compare_select(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_CS_EN_REG);
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reg_val |= (GP_CH0_CMP_EN << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_CS_EN_REG);
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}
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static void gpadc_compare_deselect(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_CTRL_REG);
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reg_val &= ~(GP_CH0_CMP_EN << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_CTRL_REG);
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}
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static void gpadc_channel_enable_lowirq(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_DATAL_INTC_REG);
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reg_val |= (0x01 << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_DATAL_INTC_REG);
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}
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static void gpadc_channel_disable_lowirq(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_DATAL_INTC_REG);
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reg_val &= ~(0x01 << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_DATAL_INTC_REG);
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}
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static void gpadc_channel_compare_lowdata(hal_gpadc_channel_t channal,
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uint32_t low_uv)
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{
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uint32_t reg_val = 0, low = 0, unit = 0;
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hal_gpadc_t *gpadc = &hal_gpadc;
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/* analog voltage range 0~1.8v, 12bits sample rate, unit=1.8v/(2^12) */
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unit = VOL_RANGE / 4096; /* 12bits sample rate */
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low = low_uv / unit;
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if (low > VOL_VALUE_MASK)
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{
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low = VOL_VALUE_MASK;
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}
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_CH0_CMP_DATA_REG + 4 * channal);
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reg_val &= ~VOL_VALUE_MASK;
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reg_val |= (low & VOL_VALUE_MASK);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_CH0_CMP_DATA_REG + 4 * channal);
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}
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static void gpadc_channel_enable_highirq(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_DATAH_INTC_REG);
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reg_val |= (1 << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_DATAH_INTC_REG);
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}
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static void gpadc_channel_disable_highirq(hal_gpadc_channel_t channal)
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{
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uint32_t reg_val;
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hal_gpadc_t *gpadc = &hal_gpadc;
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_DATAH_INTC_REG);
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reg_val &= ~(1 << channal);
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_DATAH_INTC_REG);
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}
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static void gpadc_channel_compare_highdata(hal_gpadc_channel_t channal,
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uint32_t hig_uv)
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{
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uint32_t reg_val = 0, hig_val = 0, unit_val = 0;
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hal_gpadc_t *gpadc = &hal_gpadc;
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/* anolog voltage range 0~1.8v, 12bits sample rate, unit=1.8v/(2^12) */
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unit_val = VOL_RANGE / 4096; /* 12bits sample rate */
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hig_val = hig_uv / unit_val;
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if (hig_val > VOL_VALUE_MASK)
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{
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hig_val = VOL_VALUE_MASK;
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}
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reg_val = readl((unsigned long)(gpadc->reg_base) + GP_CH0_CMP_DATA_REG + 4 * channal);
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reg_val &= ~(VOL_VALUE_MASK << 16);
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reg_val |= (hig_val & VOL_VALUE_MASK) << 16;
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writel(reg_val, (unsigned long)(gpadc->reg_base) + GP_CH0_CMP_DATA_REG + 4 * channal);
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}
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/* clk_in: source clock, round_clk: sample rate */
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static void gpadc_sample_rate_set(uint32_t reg_base, uint32_t clk_in,
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uint32_t round_clk)
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{
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uint32_t div, reg_val;
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if (round_clk > clk_in)
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{
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GPADC_ERR("invalid round clk!");
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}
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div = clk_in / round_clk - 1 ;
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reg_val = readl((unsigned long)(reg_base) + GP_SR_REG);
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reg_val &= ~GP_SR_CON;
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reg_val |= (div << 16);
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writel(reg_val, (unsigned long)(reg_base) + GP_SR_REG);
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}
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static void gpadc_calibration_enable(uint32_t reg_base)
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{
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uint32_t reg_val;
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reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG);
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reg_val |= GP_CALI_EN;
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writel(reg_val, (unsigned long)(reg_base) + GP_CTRL_REG);
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}
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static void gpadc_mode_select(uint32_t reg_base,
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enum gp_select_mode mode)
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{
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uint32_t reg_val;
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reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG);
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reg_val &= ~GP_MODE_SELECT;
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reg_val |= (mode << 18);
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writel(reg_val, (unsigned long)(reg_base) + GP_CTRL_REG);
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}
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/* enable gpadc function, true:enable, false:disable */
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static void gpadc_enable(uint32_t reg_base)
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{
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uint32_t reg_val = 0;
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reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG);
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reg_val |= GP_ADC_EN;
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writel(reg_val, (unsigned long)(reg_base) + GP_CTRL_REG);
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}
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/* enable gpadc function, true:enable, false:disable */
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static void gpadc_disable(uint32_t reg_base)
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{
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uint32_t reg_val = 0;
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reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG);
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reg_val &= ~GP_ADC_EN;
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writel(reg_val, (unsigned long)(reg_base) + GP_CTRL_REG);
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}
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static uint32_t gpadc_read_channel_irq_enable(uint32_t reg_base)
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{
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return readl((unsigned long)(reg_base) + GP_DATA_INTC_REG);
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}
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static uint32_t gpadc_read_channel_lowirq_enable(uint32_t reg_base)
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{
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return readl((unsigned long)(reg_base) + GP_DATAL_INTC_REG);
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}
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static uint32_t gpadc_read_channel_highirq_enable(uint32_t reg_base)
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{
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return readl((unsigned long)(reg_base) + GP_DATAH_INTC_REG);
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}
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static uint32_t gpadc_channel_irq_status(uint32_t reg_base)
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{
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return readl((unsigned long)(reg_base) + GP_DATA_INTS_REG);
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}
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static void gpadc_channel_clear_irq(uint32_t reg_base, uint32_t flags)
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{
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writel(flags, (unsigned long)(reg_base) + GP_DATA_INTS_REG);
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}
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static uint32_t gpadc_channel_lowirq_status(uint32_t reg_base)
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{
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return readl((unsigned long)(reg_base) + GP_DATAL_INTS_REG);
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}
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static void gpadc_channel_clear_lowirq(uint32_t reg_base, uint32_t flags)
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{
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writel(flags, (unsigned long)(reg_base) + GP_DATAL_INTS_REG);
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}
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static uint32_t gpadc_channel_highirq_status(uint32_t reg_base)
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{
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return readl((unsigned long)(reg_base) + GP_DATAH_INTS_REG);
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}
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static void gpadc_channel_clear_highirq(uint32_t reg_base, uint32_t flags)
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{
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writel(flags, (unsigned long)(reg_base) + GP_DATAH_INTS_REG);
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}
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static int gpadc_read_data(uint32_t reg_base, hal_gpadc_channel_t channal)
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{
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return readl((unsigned long)(reg_base) + GP_CH0_DATA_REG + 4 * channal) & GP_CH_DATA_MASK;
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}
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int hal_gpadc_callback(uint32_t data_type, uint32_t data)
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{
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GPADC_INFO("gpadc interrupt, data_type is %ld", data_type);
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return 0;
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}
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static irqreturn_t gpadc_handler(int irq, void *dev)
|
||
|
|
{
|
||
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|
hal_gpadc_t *gpadc = (hal_gpadc_t *)dev;
|
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|
|
|
||
|
|
uint32_t reg_val, reg_low, reg_high;
|
||
|
|
uint32_t reg_enable, reg_enable_low, reg_enable_high;
|
||
|
|
uint32_t i, data = 0;
|
||
|
|
|
||
|
|
reg_enable = gpadc_read_channel_irq_enable(gpadc->reg_base);
|
||
|
|
reg_enable_low = gpadc_read_channel_lowirq_enable(gpadc->reg_base);
|
||
|
|
reg_enable_high = gpadc_read_channel_highirq_enable(gpadc->reg_base);
|
||
|
|
|
||
|
|
reg_val = gpadc_channel_irq_status(gpadc->reg_base);
|
||
|
|
gpadc_channel_clear_irq(gpadc->reg_base, reg_val);
|
||
|
|
reg_low = gpadc_channel_lowirq_status(gpadc->reg_base);
|
||
|
|
gpadc_channel_clear_lowirq(gpadc->reg_base, reg_val);
|
||
|
|
reg_high = gpadc_channel_highirq_status(gpadc->reg_base);
|
||
|
|
gpadc_channel_clear_highirq(gpadc->reg_base, reg_val);
|
||
|
|
|
||
|
|
for (i = 0; i < gpadc->channel_num; i++)
|
||
|
|
{
|
||
|
|
if (reg_low & (1 << i) & reg_enable_low)
|
||
|
|
{
|
||
|
|
data = gpadc_read_data(gpadc->reg_base, i);
|
||
|
|
gpadc_channel_enable_highirq(i);
|
||
|
|
|
||
|
|
if (gpadc->callback[i])
|
||
|
|
{
|
||
|
|
gpadc->callback[i](GPADC_DOWN, data);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (reg_high & (1 << i) & reg_enable_high)
|
||
|
|
{
|
||
|
|
gpadc_channel_disable_highirq(i);
|
||
|
|
gpadc->callback[i](GPADC_UP, data);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
hal_gpadc_status_t hal_gpadc_register_callback(hal_gpadc_channel_t channal,
|
||
|
|
gpadc_callback_t user_callback)
|
||
|
|
{
|
||
|
|
hal_gpadc_t *gpadc = &hal_gpadc;
|
||
|
|
|
||
|
|
if (gpadc_channel_check_valid(channal))
|
||
|
|
{
|
||
|
|
return GPADC_CHANNEL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (user_callback == NULL)
|
||
|
|
{
|
||
|
|
return GPADC_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpadc->callback[channal] = user_callback;
|
||
|
|
|
||
|
|
return GPADC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
hal_gpadc_status_t hal_gpadc_channel_init(hal_gpadc_channel_t channal)
|
||
|
|
{
|
||
|
|
hal_gpadc_t *gpadc = &hal_gpadc;
|
||
|
|
|
||
|
|
if (gpadc_channel_check_valid(channal))
|
||
|
|
{
|
||
|
|
return GPADC_CHANNEL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpadc_channel_select(channal);
|
||
|
|
gpadc_compare_select(channal);
|
||
|
|
gpadc_channel_enable_lowirq(channal);
|
||
|
|
gpadc_channel_compare_lowdata(channal, COMPARE_LOWDATA);
|
||
|
|
gpadc_channel_compare_highdata(channal, COMPARE_HIGDATA);
|
||
|
|
|
||
|
|
return GPADC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
hal_gpadc_status_t hal_gpadc_channel_exit(hal_gpadc_channel_t channal)
|
||
|
|
{
|
||
|
|
hal_gpadc_t *gpadc = &hal_gpadc;
|
||
|
|
|
||
|
|
if (gpadc_channel_check_valid(channal))
|
||
|
|
{
|
||
|
|
return GPADC_CHANNEL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpadc_channel_deselect(channal);
|
||
|
|
gpadc_compare_deselect(channal);
|
||
|
|
gpadc_channel_disable_lowirq(channal);
|
||
|
|
|
||
|
|
return GPADC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void hal_gpadc_setup(hal_gpadc_t *gpadc)
|
||
|
|
{
|
||
|
|
uint8_t i;
|
||
|
|
|
||
|
|
gpadc->reg_base = GPADC_BASE;
|
||
|
|
gpadc->channel_num = CHANNEL_NUM;
|
||
|
|
gpadc->irq_num = SUNXI_GPADC_IRQ;
|
||
|
|
gpadc->sample_rate = DEFAULT_SR;
|
||
|
|
#if defined(CONFIG_SOC_SUN20IW1)
|
||
|
|
gpadc->bus_clk = CLK_BUS_GPADC;
|
||
|
|
gpadc->rst_clk = RST_BUS_GPADC;
|
||
|
|
#else
|
||
|
|
gpadc->pclk = HAL_CLK_SRC_HOSC24M;
|
||
|
|
gpadc->mclk = HAL_CLK_PERIPH_GPADC;
|
||
|
|
#endif
|
||
|
|
gpadc->mode = GP_CONTINUOUS_MODE;
|
||
|
|
|
||
|
|
for (i = 0; i < gpadc->channel_num; i++)
|
||
|
|
{
|
||
|
|
gpadc->callback[i] = hal_gpadc_callback;
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
int hal_gpadc_init(void)
|
||
|
|
{
|
||
|
|
hal_gpadc_t *gpadc = &hal_gpadc;
|
||
|
|
|
||
|
|
|
||
|
|
hal_gpadc_setup(gpadc);
|
||
|
|
|
||
|
|
if (hal_gpadc_clk_init(gpadc))
|
||
|
|
{
|
||
|
|
GPADC_ERR("gpadc init clk error");
|
||
|
|
return GPADC_CLK_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
GPADC_INFO("gpadc set sample rate");
|
||
|
|
gpadc_sample_rate_set(gpadc->reg_base, OSC_24MHZ, gpadc->sample_rate);
|
||
|
|
|
||
|
|
if (request_irq(gpadc->irq_num, gpadc_handler, IRQF_NO_SUSPEND, "gpadc", gpadc))
|
||
|
|
{
|
||
|
|
return GPADC_IRQ_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
enable_irq(gpadc->irq_num);
|
||
|
|
|
||
|
|
GPADC_INFO("gpadc enable calibration");
|
||
|
|
gpadc_calibration_enable(gpadc->reg_base);
|
||
|
|
gpadc_mode_select(gpadc->reg_base, gpadc->mode);
|
||
|
|
gpadc_enable(gpadc->reg_base);
|
||
|
|
|
||
|
|
return GPADC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
hal_gpadc_status_t hal_gpadc_deinit(void)
|
||
|
|
{
|
||
|
|
disable_irq(hal_gpadc.irq_num);
|
||
|
|
#if defined(CONFIG_SOC_SUN20IW1)
|
||
|
|
hal_clock_disable(hal_gpadc.mbus_clk);
|
||
|
|
#else
|
||
|
|
hal_clock_disable(hal_gpadc.mclk);
|
||
|
|
#endif
|
||
|
|
return GPADC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
//device_initcall(hal_gpadc_init);
|