599 lines
21 KiB
C
599 lines
21 KiB
C
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/**************************************************************************//**
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* @file qspi.c
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* @brief NUC980 series QSPI driver source file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "nuc980.h"
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#include "nu_qspi.h"
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup QSPI_Driver QSPI Driver
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@{
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*/
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/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
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@{
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*/
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/**
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* @brief This function make QSPI module be ready to transfer.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER)
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* @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3)
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* @param[in] u32DataWidth Decides the data width of a QSPI transaction.
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* @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
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* @return Actual frequency of QSPI peripheral clock.
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* @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
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* slave selection function is disabled.
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* In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0.
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* The actual clock rate may be different from the target QSPI clock rate.
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* For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the
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* actual QSPI clock rate will be 6MHz.
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* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
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* @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
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* @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
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* @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate.
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*/
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uint32_t QSPI_Open(QSPI_T *qspi,
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uint32_t u32MasterSlave,
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uint32_t u32QSPIMode,
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uint32_t u32DataWidth,
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uint32_t u32BusClock)
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{
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uint32_t u32RetValue = 0U;
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if (u32DataWidth == 32U)
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{
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u32DataWidth = 0U;
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}
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if (u32MasterSlave == QSPI_MASTER)
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{
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/* Default setting: slave selection signal is active low; disable automatic slave selection function. */
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qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
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/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
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qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
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/* Set DIVIDER */
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qspi->CLKDIV = ((150000000U / u32BusClock) - 1U);
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}
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else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */
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{
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/* Default setting: slave selection signal is low level active. */
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qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
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/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
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qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
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/* Set DIVIDER = 0 */
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qspi->CLKDIV = 0U;
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}
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return u32RetValue;
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}
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/**
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* @brief Disable QSPI controller.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @return None
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* @details This function will reset QSPI controller.
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*/
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void QSPI_Close(QSPI_T *qspi)
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{
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/* Reset QSPI */
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}
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/**
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* @brief Clear RX FIFO buffer.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @return None
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* @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1.
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*/
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void QSPI_ClearRxFIFO(QSPI_T *qspi)
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{
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qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk;
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}
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/**
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* @brief Clear TX FIFO buffer.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @return None
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* @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1.
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* @note The TX shift register will not be cleared.
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*/
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void QSPI_ClearTxFIFO(QSPI_T *qspi)
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{
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qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk;
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}
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/**
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* @brief Disable the automatic slave selection function.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @return None
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* @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
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*/
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void QSPI_DisableAutoSS(QSPI_T *qspi)
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{
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qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk);
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}
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/**
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* @brief Enable the automatic slave selection function.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS)
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* @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW)
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* @return None
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* @details This function will enable the automatic slave selection function. Only available in Master mode.
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* The slave selection pin and the active level will be set in this function.
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*/
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void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
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{
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qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk);
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}
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/**
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* @brief Set the QSPI bus clock.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
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* @return Actual frequency of QSPI bus clock.
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* @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate.
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* For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock
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* rate will be 6 MHz.
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* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
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* @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
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* @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
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*/
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uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
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{
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return 0;
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}
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/**
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* @brief Configure FIFO threshold setting.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
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* @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
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* @return None
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* @details Set TX FIFO threshold and RX FIFO threshold configurations.
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*/
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void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
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{
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qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) |
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(u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) |
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(u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos);
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}
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/**
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* @brief Get the actual frequency of QSPI bus clock. Only available in Master mode.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @return Actual QSPI bus clock frequency in Hz.
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* @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode.
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*/
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uint32_t QSPI_GetBusClock(QSPI_T *qspi)
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{
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/* Return QSPI bus clock rate */
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return 0;
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}
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/**
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* @brief Enable interrupt function.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @param[in] u32Mask The combination of all related interrupt enable bits.
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* Each bit corresponds to a interrupt enable bit.
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* This parameter decides which interrupts will be enabled. It is combination of:
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* - \ref QSPI_UNIT_INT_MASK
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* - \ref QSPI_SSACT_INT_MASK
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* - \ref QSPI_SSINACT_INT_MASK
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* - \ref QSPI_SLVUR_INT_MASK
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* - \ref QSPI_SLVBE_INT_MASK
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* - \ref QSPI_TXUF_INT_MASK
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* - \ref QSPI_FIFO_TXTH_INT_MASK
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* - \ref QSPI_FIFO_RXTH_INT_MASK
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* - \ref QSPI_FIFO_RXOV_INT_MASK
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* - \ref QSPI_FIFO_RXTO_INT_MASK
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*
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* @return None
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* @details Enable QSPI related interrupts specified by u32Mask parameter.
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*/
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void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
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{
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/* Enable unit transfer interrupt flag */
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if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
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{
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qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
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}
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/* Enable slave selection signal active interrupt flag */
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if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
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{
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qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
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}
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/* Enable slave selection signal inactive interrupt flag */
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if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
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{
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qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
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}
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/* Enable slave TX under run interrupt flag */
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if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
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{
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qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
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}
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/* Enable slave bit count error interrupt flag */
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if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
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{
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qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
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}
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/* Enable slave TX underflow interrupt flag */
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if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
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{
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qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
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}
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/* Enable TX threshold interrupt flag */
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if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
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{
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qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
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}
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/* Enable RX threshold interrupt flag */
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if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
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{
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qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
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}
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/* Enable RX overrun interrupt flag */
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if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
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{
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qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
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}
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/* Enable RX time-out interrupt flag */
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if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
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{
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qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
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}
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}
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/**
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* @brief Disable interrupt function.
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* @param[in] qspi The pointer of the specified QSPI module.
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* @param[in] u32Mask The combination of all related interrupt enable bits.
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* Each bit corresponds to a interrupt bit.
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* This parameter decides which interrupts will be disabled. It is combination of:
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* - \ref QSPI_UNIT_INT_MASK
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* - \ref QSPI_SSACT_INT_MASK
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* - \ref QSPI_SSINACT_INT_MASK
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* - \ref QSPI_SLVUR_INT_MASK
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* - \ref QSPI_SLVBE_INT_MASK
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* - \ref QSPI_TXUF_INT_MASK
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* - \ref QSPI_FIFO_TXTH_INT_MASK
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* - \ref QSPI_FIFO_RXTH_INT_MASK
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* - \ref QSPI_FIFO_RXOV_INT_MASK
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* - \ref QSPI_FIFO_RXTO_INT_MASK
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*
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* @return None
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* @details Disable QSPI related interrupts specified by u32Mask parameter.
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*/
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void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
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{
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/* Disable unit transfer interrupt flag */
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if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
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{
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qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
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}
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/* Disable slave selection signal active interrupt flag */
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if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
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{
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qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
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}
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/* Disable slave selection signal inactive interrupt flag */
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if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
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{
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qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
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}
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/* Disable slave TX under run interrupt flag */
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if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
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{
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qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
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}
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/* Disable slave bit count error interrupt flag */
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if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
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{
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qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
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}
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/* Disable slave TX underflow interrupt flag */
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if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
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{
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qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
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}
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/* Disable TX threshold interrupt flag */
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if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
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{
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|
|
qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable RX threshold interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable RX overrun interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable RX time-out interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get interrupt flag.
|
||
|
|
* @param[in] qspi The pointer of the specified QSPI module.
|
||
|
|
* @param[in] u32Mask The combination of all related interrupt sources.
|
||
|
|
* Each bit corresponds to a interrupt source.
|
||
|
|
* This parameter decides which interrupt flags will be read. It is combination of:
|
||
|
|
* - \ref QSPI_UNIT_INT_MASK
|
||
|
|
* - \ref QSPI_SSACT_INT_MASK
|
||
|
|
* - \ref QSPI_SSINACT_INT_MASK
|
||
|
|
* - \ref QSPI_SLVUR_INT_MASK
|
||
|
|
* - \ref QSPI_SLVBE_INT_MASK
|
||
|
|
* - \ref QSPI_TXUF_INT_MASK
|
||
|
|
* - \ref QSPI_FIFO_TXTH_INT_MASK
|
||
|
|
* - \ref QSPI_FIFO_RXTH_INT_MASK
|
||
|
|
* - \ref QSPI_FIFO_RXOV_INT_MASK
|
||
|
|
* - \ref QSPI_FIFO_RXTO_INT_MASK
|
||
|
|
*
|
||
|
|
* @return Interrupt flags of selected sources.
|
||
|
|
* @details Get QSPI related interrupt flags specified by u32Mask parameter.
|
||
|
|
*/
|
||
|
|
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
|
||
|
|
{
|
||
|
|
uint32_t u32IntFlag = 0U, u32TmpVal;
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk;
|
||
|
|
/* Check unit transfer interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_UNIT_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk;
|
||
|
|
/* Check slave selection signal active interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_SSACT_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk;
|
||
|
|
/* Check slave selection signal inactive interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_SSINACT_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk;
|
||
|
|
/* Check slave TX under run interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_SLVUR_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk;
|
||
|
|
/* Check slave bit count error interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_SLVBE_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk;
|
||
|
|
/* Check slave TX underflow interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_TXUF_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk;
|
||
|
|
/* Check TX threshold interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk;
|
||
|
|
/* Check RX threshold interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk;
|
||
|
|
/* Check RX overrun interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk;
|
||
|
|
/* Check RX time-out interrupt flag */
|
||
|
|
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
|
||
|
|
{
|
||
|
|
u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
return u32IntFlag;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear interrupt flag.
|
||
|
|
* @param[in] qspi The pointer of the specified QSPI module.
|
||
|
|
* @param[in] u32Mask The combination of all related interrupt sources.
|
||
|
|
* Each bit corresponds to a interrupt source.
|
||
|
|
* This parameter decides which interrupt flags will be cleared. It could be the combination of:
|
||
|
|
* - \ref QSPI_UNIT_INT_MASK
|
||
|
|
* - \ref QSPI_SSACT_INT_MASK
|
||
|
|
* - \ref QSPI_SSINACT_INT_MASK
|
||
|
|
* - \ref QSPI_SLVUR_INT_MASK
|
||
|
|
* - \ref QSPI_SLVBE_INT_MASK
|
||
|
|
* - \ref QSPI_TXUF_INT_MASK
|
||
|
|
* - \ref QSPI_FIFO_RXOV_INT_MASK
|
||
|
|
* - \ref QSPI_FIFO_RXTO_INT_MASK
|
||
|
|
*
|
||
|
|
* @return None
|
||
|
|
* @details Clear QSPI related interrupt flags specified by u32Mask parameter.
|
||
|
|
*/
|
||
|
|
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
|
||
|
|
{
|
||
|
|
if (u32Mask & QSPI_UNIT_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
|
||
|
|
}
|
||
|
|
|
||
|
|
if (u32Mask & QSPI_SSACT_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
|
||
|
|
}
|
||
|
|
|
||
|
|
if (u32Mask & QSPI_SSINACT_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
|
||
|
|
}
|
||
|
|
|
||
|
|
if (u32Mask & QSPI_SLVUR_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
|
||
|
|
}
|
||
|
|
|
||
|
|
if (u32Mask & QSPI_SLVBE_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
|
||
|
|
}
|
||
|
|
|
||
|
|
if (u32Mask & QSPI_TXUF_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
|
||
|
|
}
|
||
|
|
|
||
|
|
if (u32Mask & QSPI_FIFO_RXOV_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
|
||
|
|
}
|
||
|
|
|
||
|
|
if (u32Mask & QSPI_FIFO_RXTO_INT_MASK)
|
||
|
|
{
|
||
|
|
qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get QSPI status.
|
||
|
|
* @param[in] qspi The pointer of the specified QSPI module.
|
||
|
|
* @param[in] u32Mask The combination of all related sources.
|
||
|
|
* Each bit corresponds to a source.
|
||
|
|
* This parameter decides which flags will be read. It is combination of:
|
||
|
|
* - \ref QSPI_BUSY_MASK
|
||
|
|
* - \ref QSPI_RX_EMPTY_MASK
|
||
|
|
* - \ref QSPI_RX_FULL_MASK
|
||
|
|
* - \ref QSPI_TX_EMPTY_MASK
|
||
|
|
* - \ref QSPI_TX_FULL_MASK
|
||
|
|
* - \ref QSPI_TXRX_RESET_MASK
|
||
|
|
* - \ref QSPI_QSPIEN_STS_MASK
|
||
|
|
* - \ref QSPI_SSLINE_STS_MASK
|
||
|
|
*
|
||
|
|
* @return Flags of selected sources.
|
||
|
|
* @details Get QSPI related status specified by u32Mask parameter.
|
||
|
|
*/
|
||
|
|
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
|
||
|
|
{
|
||
|
|
uint32_t u32Flag = 0U, u32TmpValue;
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk;
|
||
|
|
/* Check busy status */
|
||
|
|
if ((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_BUSY_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk;
|
||
|
|
/* Check RX empty flag */
|
||
|
|
if ((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_RX_EMPTY_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk;
|
||
|
|
/* Check RX full flag */
|
||
|
|
if ((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_RX_FULL_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk;
|
||
|
|
/* Check TX empty flag */
|
||
|
|
if ((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_TX_EMPTY_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk;
|
||
|
|
/* Check TX full flag */
|
||
|
|
if ((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_TX_FULL_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk;
|
||
|
|
/* Check TX/RX reset flag */
|
||
|
|
if ((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_TXRX_RESET_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk;
|
||
|
|
/* Check QSPIEN flag */
|
||
|
|
if ((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_QSPIEN_STS_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk;
|
||
|
|
/* Check QSPIx_SS line status */
|
||
|
|
if ((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
|
||
|
|
{
|
||
|
|
u32Flag |= QSPI_SSLINE_STS_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
return u32Flag;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
|
||
|
|
|
||
|
|
/*@}*/ /* end of group QSPI_Driver */
|
||
|
|
|
||
|
|
/*@}*/ /* end of group Standard_Driver */
|
||
|
|
|
||
|
|
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|