542 lines
34 KiB
C
542 lines
34 KiB
C
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/****************************************************************************//**
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* @file i2c.h
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* @version V1.00
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* @brief NUC980 series I2C driver header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __NU_I2C_H__
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#define __NU_I2C_H__
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "nuc980.h"
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup I2C_Driver I2C Driver
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@{
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*/
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/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* I2C_CTL constant definitions. */
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/*---------------------------------------------------------------------------------------------------------*/
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#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */
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#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */
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#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */
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#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */
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#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */
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#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */
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#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
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#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
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#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
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/*---------------------------------------------------------------------------------------------------------*/
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/* I2C GCMode constant definitions. */
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/*---------------------------------------------------------------------------------------------------------*/
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#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
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#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
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/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
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typedef struct
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{
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volatile uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
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volatile uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
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volatile uint32_t DAT; /*!< [0x0008] I2C Data Register */
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volatile uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
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volatile uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
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volatile uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
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volatile uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
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volatile uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
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volatile uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
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volatile uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
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volatile uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
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volatile uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
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volatile uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
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volatile uint32_t RESERVE0[2];
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volatile uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
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volatile uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
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volatile uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
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volatile uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
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volatile uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
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volatile uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
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volatile uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
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volatile uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
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volatile uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
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volatile uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
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volatile uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
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volatile uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
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} I2C_T;
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#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
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#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */
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#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
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#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */
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#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
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#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */
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#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
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#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */
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#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
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#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
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#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
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#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
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#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
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#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
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#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
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#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
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#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
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#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
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#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
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#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */
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#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
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#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
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#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
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#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
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#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
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#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
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#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
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#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
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#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
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#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
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#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
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#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
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#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
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#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
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#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
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#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
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#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
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#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
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#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
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#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
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#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
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#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
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#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
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#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
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#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
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#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
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#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
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#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
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#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
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#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
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#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
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#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
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#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
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#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
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#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
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#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
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#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
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#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
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#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
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#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
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#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
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#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
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#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
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#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
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#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
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#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
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#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
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#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
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#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
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#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
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#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
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#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
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#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
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#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
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#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
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#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
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#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
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#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
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#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
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#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
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#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
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#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
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#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
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#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
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#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
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#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
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#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
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#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
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#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
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#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
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#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
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#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
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#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
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#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
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#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
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#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
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#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
|
||
|
|
#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
|
||
|
|
#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
|
||
|
|
#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
|
||
|
|
#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
|
||
|
|
#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
|
||
|
|
#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
|
||
|
|
#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
|
||
|
|
#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
|
||
|
|
#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
|
||
|
|
#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
|
||
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|
||
|
|
#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
|
||
|
|
#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
|
||
|
|
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
|
||
|
|
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
|
||
|
|
#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
|
||
|
|
#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
|
||
|
|
#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
|
||
|
|
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
|
||
|
|
#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
|
||
|
|
#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
|
||
|
|
#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
|
||
|
|
|
||
|
|
#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
|
||
|
|
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
|
||
|
|
|
||
|
|
#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
|
||
|
|
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
|
||
|
|
|
||
|
|
#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
|
||
|
|
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
|
||
|
|
|
||
|
|
#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
|
||
|
|
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
|
||
|
|
|
||
|
|
|
||
|
|
#define I2C0 ((I2C_T *) I2C0_BA)
|
||
|
|
#define I2C1 ((I2C_T *) I2C1_BA)
|
||
|
|
#define I2C2 ((I2C_T *) I2C2_BA)
|
||
|
|
#define I2C3 ((I2C_T *) I2C3_BA)
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
|
||
|
|
@{
|
||
|
|
*/
|
||
|
|
/**
|
||
|
|
* @brief The macro is used to set I2C bus condition at One Time
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
* @param[in] u8Ctrl A byte writes to I2C control register
|
||
|
|
*
|
||
|
|
* @return None
|
||
|
|
*
|
||
|
|
* @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief The macro is used to set START condition of I2C Bus
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
*
|
||
|
|
* @return None
|
||
|
|
*
|
||
|
|
* @details Set the I2C bus START condition in I2C_CTL register.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief The macro is used to wait I2C bus status get ready
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
*
|
||
|
|
* @return None
|
||
|
|
*
|
||
|
|
* @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief The macro is used to Read I2C Bus Data Register
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
*
|
||
|
|
* @return A byte of I2C data register
|
||
|
|
*
|
||
|
|
* @details I2C controller read data from bus and save it in I2CDAT register.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_GET_DATA(i2c) ((i2c)->DAT)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Write a Data to I2C Data Register
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
* @param[in] u8Data A byte that writes to data register
|
||
|
|
*
|
||
|
|
* @return None
|
||
|
|
*
|
||
|
|
* @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get I2C Bus status code
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
*
|
||
|
|
* @return I2C status code
|
||
|
|
*
|
||
|
|
* @details To get this status code to monitor I2C bus event.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get Time-out flag from I2C Bus
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
*
|
||
|
|
* @retval 0 I2C Bus time-out is not happened
|
||
|
|
* @retval 1 I2C Bus time-out is happened
|
||
|
|
*
|
||
|
|
* @details When I2C bus occurs time-out event, the time-out flag will be set.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief To get wake-up flag from I2C Bus
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
*
|
||
|
|
* @retval 0 Chip is not woken-up from power-down mode
|
||
|
|
* @retval 1 Chip is woken-up from power-down mode
|
||
|
|
*
|
||
|
|
* @details I2C bus occurs wake-up event, wake-up flag will be set.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief To clear wake-up flag
|
||
|
|
*
|
||
|
|
* @param[in] i2c Specify I2C port
|
||
|
|
*
|
||
|
|
* @return None
|
||
|
|
*
|
||
|
|
* @details If wake-up flag is set, use this macro to clear it.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable RX PDMA function.
|
||
|
|
* @param[in] i2c The pointer of the specified I2C module.
|
||
|
|
* @return None.
|
||
|
|
* @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable TX PDMA function.
|
||
|
|
* @param[in] i2c The pointer of the specified I2C module.
|
||
|
|
* @return None.
|
||
|
|
* @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable RX PDMA transfer.
|
||
|
|
* @param[in] i2c The pointer of the specified I2C module.
|
||
|
|
* @return None.
|
||
|
|
* @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable TX PDMA transfer.
|
||
|
|
* @param[in] i2c The pointer of the specified I2C module.
|
||
|
|
* @return None.
|
||
|
|
* @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable PDMA stretch function.
|
||
|
|
* @param[in] i2c The pointer of the specified I2C module.
|
||
|
|
* @return None.
|
||
|
|
* @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable PDMA stretch function.
|
||
|
|
* @param[in] i2c The pointer of the specified I2C module.
|
||
|
|
* @return None.
|
||
|
|
* @details I2C will send STOP after PDMA transfers done automatically.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Reset PDMA function.
|
||
|
|
* @param[in] i2c The pointer of the specified I2C module.
|
||
|
|
* @return None.
|
||
|
|
* @details I2C PDMA engine will be reset after this function is called.
|
||
|
|
* \hideinitializer
|
||
|
|
*/
|
||
|
|
#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------------------------------------*/
|
||
|
|
/* inline functions */
|
||
|
|
/*---------------------------------------------------------------------------------------------------------*/
|
||
|
|
|
||
|
|
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
|
||
|
|
void I2C_STOP(I2C_T *i2c);
|
||
|
|
|
||
|
|
void I2C_ClearTimeoutFlag(I2C_T *i2c);
|
||
|
|
void I2C_Close(I2C_T *i2c);
|
||
|
|
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
|
||
|
|
void I2C_DisableInt(I2C_T *i2c);
|
||
|
|
void I2C_EnableInt(I2C_T *i2c);
|
||
|
|
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
|
||
|
|
uint32_t I2C_GetIntFlag(I2C_T *i2c);
|
||
|
|
uint32_t I2C_GetStatus(I2C_T *i2c);
|
||
|
|
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
|
||
|
|
uint8_t I2C_GetData(I2C_T *i2c);
|
||
|
|
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
|
||
|
|
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
|
||
|
|
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
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void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
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void I2C_DisableTimeout(I2C_T *i2c);
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void I2C_EnableWakeup(I2C_T *i2c);
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void I2C_DisableWakeup(I2C_T *i2c);
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void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
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uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
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uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
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uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
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uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
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uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
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uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
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uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
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uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
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uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
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uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
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uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
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uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
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/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group I2C_Driver */
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/*@}*/ /* end of group Standard_Driver */
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#endif
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/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
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