42 lines
1.5 KiB
C
42 lines
1.5 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-18 luobeihai first version
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*/
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#ifndef __DRV_SDRAM_H__
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#define __DRV_SDRAM_H__
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/* parameters for sdram peripheral */
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/* Bank1 or Bank2 */
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#define SDRAM_TARGET_BANK 1
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/* apm32f407 Bank Addr: 0x60000000 */
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#define SDRAM_BANK_ADDR ((uint32_t)0x60000000)
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/* data width: 8, 16, 32 */
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#define SDRAM_DATA_WIDTH 16
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/* column bit numbers */
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#define SDRAM_COLUMN_BITS DMC_COL_WIDTH_8
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/* row bit numbers */
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#define SDRAM_ROW_BITS DMC_ROW_WIDTH_11
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#define SDRAM_SIZE ((uint32_t)0x200000)
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/* memory mode register */
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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#endif
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