398 lines
13 KiB
C
398 lines
13 KiB
C
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/* ------------------------------------------
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* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2016.05
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* \date 2016-09-08
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* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup ARC_HAL_MISC
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* \brief header file for arc feature configuration
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*/
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/**
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* \addtogroup ARC_HAL_MISC
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* @{
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*/
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#ifndef _ARC_FEATURE_CONFIG_H_
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#define _ARC_FEATURE_CONFIG_H_
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// Enable core_config.h in EMSK OSP
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//#ifdef EMBARC_TCF_GENERATED
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#include "arc_core_config.h"
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//#endif
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/** ARC baseline instruction set version number */
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#if !defined(_ARCVER)
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#if defined(core_config_cir_identity_arcver)
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#define _ARCVER core_config_cir_identity_arcver
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#else
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#define _ARCVER 0x42
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#endif
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#endif
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/** ARC CPU Clock Frequency in Hz unit */
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#if !defined(ARC_FEATURE_CPU_CLOCK_FREQ)
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#if defined(core_config_clock_speed)
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#define ARC_FEATURE_CPU_CLOCK_FREQ (core_config_clock_speed*1000000)
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#endif
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#endif
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/** ARC PC size */
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#if !defined(ARC_FEATURE_PC_SIZE)
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#if defined(core_config_pc_size)
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#define ARC_FEATURE_PC_SIZE core_config_pc_size
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#else
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#define ARC_FEATURE_PC_SIZE 32
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#endif
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#endif
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/** ARC LPC size */
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#if !defined(ARC_FEATURE_LPC_SIZE)
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#if defined(core_config_lpc_size)
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#define ARC_FEATURE_LPC_SIZE core_config_lpc_size
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#else
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#define ARC_FEATURE_LPC_SIZE 32
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#endif
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#endif
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/** ARC Addr size */
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#if !defined(ARC_FEATURE_ADDR_SIZE)
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#if defined(core_config_addr_size)
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#define ARC_FEATURE_ADDR_SIZE core_config_addr_size
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#else
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#define ARC_FEATURE_ADDR_SIZE 32
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#endif
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#endif
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/** ARC Endian/Byte Order */
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#define ARC_FEATURE_LITTLE_ENDIAN 1234
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#define ARC_FEATURE_BIG_ENDIAN 4321
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#if !defined(ARC_FEATURE_BYTE_ORDER)
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#if defined(core_config_bcr_isa_config_b)
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#if core_config_bcr_isa_config_b == 0
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#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_LITTLE_ENDIAN
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#else
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#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_BIG_ENDIAN
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#endif
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#else
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#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_LITTLE_ENDIAN
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#endif
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#endif
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/** Reduced register option, if enabled, ARC_FEATURE_RF16 will be defined */
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#if !defined(ARC_FEATURE_RF16)
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#if defined(core_config_bcr_rf_build_e) && core_config_bcr_rf_build_e == 1
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#define ARC_FEATURE_RF16
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#endif
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#endif
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/** Unaligned access option, if enabled, ARC_FEATURE_UNALIGNED will be defined */
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#if !defined(ARC_FEATURE_UNALIGNED)
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#if defined(core_config_unaligned) && core_config_unaligned == 1
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#define ARC_FEATURE_UNALIGNED
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#endif
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#endif
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/** Code density option, if enabled, ARC_FEATURE_CODE_DENSITY will be defined */
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#if !defined(ARC_FEATURE_CODE_DENSITY)
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#if defined(core_config_code_density) && core_config_code_density == 1
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#define ARC_FEATURE_CODE_DENSITY
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#endif
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#endif
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/** The number of register file banks */
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#if !defined(ARC_FEATURE_RGF_NUM_BANKS)
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#if defined(core_config_rgf_num_banks)
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#define ARC_FEATURE_RGF_NUM_BANKS core_config_rgf_num_banks
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#else
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#define ARC_FEATURE_RGF_NUM_BANKS 1
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#endif
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#endif
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/** The number of registers replicated per register bank */
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#if !defined(ARC_FEATURE_RGF_BANKED_REGS)
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#if defined(core_config_rgf_banked_regs)
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#define ARC_FEATURE_RGF_BANKED_REGS core_config_rgf_banked_regs
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#endif
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#endif
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/** Interrupt unit presence */
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#if !defined(ARC_FEATURE_INTERRUPTS_PRESENT)
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#if defined(core_config_interrupts_present)
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#define ARC_FEATURE_INTERRUPTS_PRESENT core_config_interrupts_present
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#endif
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#endif
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/** FIRQ_OPTION configuration option, 1 for enabled, 0 for disabled */
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#if !defined(ARC_FEATURE_FIRQ)
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#if defined(core_config_bcr_irq_build_f)
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#define ARC_FEATURE_FIRQ core_config_bcr_irq_build_f
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#else
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#define ARC_FEATURE_FIRQ 0
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#endif
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#endif
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/** The number of interrupts */
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#if !defined(NUM_EXC_INT)
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#if defined(core_config_interrupts_number)
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#define NUM_EXC_INT core_config_interrupts_number
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#endif
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#endif
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/** The number of external interrupts */
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#if !defined(NUM_EXC_EXT_INT)
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#if defined(core_config_interrupts_externals)
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#define NUM_EXC_EXT_INT core_config_interrupts_externals
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#endif
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#endif
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/** The interrupt priority levels */
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#if !defined(INT_PRI_MIN)
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#if defined(core_config_interrupts_priorities)
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#define INT_PRI_MIN (-core_config_interrupts_priorities)
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#endif
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#endif
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// ARC TIMER_BUILD
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/** Timer0 present or not */
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#if !defined(ARC_FEATURE_TIMER0_PRESENT)
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#if defined(core_config_timer0)
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#define ARC_FEATURE_TIMER0_PRESENT core_config_timer0
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#define ARC_FEATURE_TIMER0_LEVEL (core_config_timer0_level-core_config_interrupts_priorities)
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#define ARC_FEATURE_TIMER0_VECTOR core_config_timer0_vector
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#endif
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#endif
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/** Timer1 present or not */
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#if !defined(ARC_FEATURE_TIMER1_PRESENT)
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#if defined(core_config_timer1)
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#define ARC_FEATURE_TIMER1_PRESENT core_config_timer1
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#define ARC_FEATURE_TIMER1_LEVEL (core_config_timer1_level-core_config_interrupts_priorities)
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#define ARC_FEATURE_TIMER1_VECTOR core_config_timer1_vector
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#endif
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#endif
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/** Secure Timer0 present or not */
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#if !defined(ARC_FEATURE_SEC_TIMER0_PRESENT)
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#if defined(core_config_sec_timer0)
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#define ARC_FEATURE_SEC_TIMER0_PRESENT core_config_sec_timer0
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#define ARC_FEATURE_SEC_TIMER0_LEVEL (core_config_sec_timer0_level-core_config_interrupts_priorities)
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#define ARC_FEATURE_SEC_TIMER0_VECTOR 20
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#endif
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#endif
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/** Secure Timer1 present or not */
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#if !defined(ARC_FEATURE_SEC_TIMER1_PRESENT)
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#if defined(core_config_sec_timer1)
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#define ARC_FEATURE_SEC_TIMER1_PRESENT core_config_sec_timer1
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#define ARC_FEATURE_SEC_TIMER1_LEVEL (core_config_sec_timer1_level-core_config_interrupts_priorities)
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#define ARC_FEATURE_SEC_TIMER1_VECTOR 21
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#endif
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#endif
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/** 64bit RTC present or not */
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#if !defined(ARC_FEATURE_RTC_PRESENT)
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#if defined(core_config_rtc)
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#define ARC_FEATURE_RTC_PRESENT core_config_rtc
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#endif
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#endif
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// Memory related definitions
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/** ICCM Presence, base address and size */
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#if !defined(ARC_FEATURE_ICCM_PRESENT)
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#if defined(core_config_iccm_present) && core_config_iccm_present == 1
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#define ARC_FEATURE_ICCM_PRESENT 1
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#define ARC_FEATURE_ICCM_BASE core_config_iccm_base
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#define ARC_FEATURE_ICCM_SIZE core_config_iccm_size
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#endif
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#endif
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/** ICCM0 Presence, base address and size */
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#if !defined(ARC_FEATURE_ICCM0_PRESENT)
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#if defined(core_config_iccm0_present) && core_config_iccm0_present == 1
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#define ARC_FEATURE_ICCM0_PRESENT 1
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#define ARC_FEATURE_ICCM0_BASE core_config_iccm0_base
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#define ARC_FEATURE_ICCM0_SIZE core_config_iccm0_size
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#endif
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#endif
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/** ICCM1 Presence, base address and size */
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#if !defined(ARC_FEATURE_ICCM1_PRESENT)
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#if defined(core_config_iccm1_present) && core_config_iccm1_present == 1
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#define ARC_FEATURE_ICCM1_PRESENT 1
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#define ARC_FEATURE_ICCM1_BASE core_config_iccm1_base
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#define ARC_FEATURE_ICCM1_SIZE core_config_iccm1_size
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#endif
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#endif
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/** DCCM Presence, base address and size */
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#if !defined(ARC_FEATURE_DCCM_PRESENT)
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#if defined(core_config_dccm_present) && core_config_dccm_present == 1
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#define ARC_FEATURE_DCCM_PRESENT 1
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#define ARC_FEATURE_DCCM_BASE core_config_dccm_base
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#define ARC_FEATURE_DCCM_SIZE core_config_dccm_size
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#ifdef core_config_dccm_interleave
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#define ARC_FEATURE_DCCM_INTERLEAVE core_config_dccm_interleave
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#endif
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#endif
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#endif
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/** Peripheral memory region(DMP) base address, if dmp configured, this macro will be defined as base address */
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#if !defined(ARC_FEATURE_DMP_PERIPHERAL)
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#if defined(core_config_cir_dmp_peripheral)
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#define ARC_FEATURE_DMP_PERIPHERAL core_config_cir_dmp_peripheral
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#endif
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#endif
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/** MPU options */
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#if !defined(ARC_FEATURE_MPU_PRESENT)
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#if defined(core_config_mpu_present) && core_config_mpu_present == 1
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#define ARC_FEATURE_MPU_PRESENT 1
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#define ARC_FEATURE_MPU_VERSION core_config_bcr_mpu_build_version
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#define ARC_FEATURE_MPU_REGIONS core_config_mpu_regions
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#ifdef core_config_bcr_mpu_build_i
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#define ARC_FEATURE_MPU_BUILD_I core_config_bcr_mpu_build_i
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#endif
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#ifdef core_config_bcr_mpu_build_s
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#define ARC_FEATURE_MPU_BUILD_S core_config_bcr_mpu_build_s
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#endif
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#endif
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#endif
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/** Secure BCR SEC_BUILD BCR */
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#if !defined(ARC_FEATURE_SEC_PRESENT)
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#if defined(core_config_bcr_sec_build)
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#define ARC_FEATURE_SEC_PRESENT 1
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#define ARC_FEATURE_SEC_VERSION core_config_bcr_sec_build_version
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#define ARC_FEATURE_SEC_BUILD_DSM core_config_bcr_sec_build_dsm
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#define ARC_FEATURE_SEC_BUILD_NSM core_config_bcr_sec_build_nsm
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#define ARC_FEATURE_SEC_BUILD_I1SM core_config_bcr_sec_build_i1sm
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#define ARC_FEATURE_SEC_BUILD_I0SM core_config_bcr_sec_build_i0sm
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#define ARC_FEATURE_SEC_BUILD_S core_config_bcr_sec_build_s
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#define ARC_FEATURE_SEC_BUILD_EI core_config_bcr_sec_build_ei
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#define ARC_FEATURE_SEC_BUILD_ED core_config_bcr_sec_build_ed
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#endif
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#endif
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#if !defined(ARC_FEATURE_SEC_MODES)
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#if defined(core_config_sec_modes)
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#define ARC_FEATURE_SEC_MODES core_config_sec_modes
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#endif
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#endif
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/** Data Cache options */
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#if !defined(ARC_FEATURE_DCACHE_PRESENT)
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#if defined(core_config_dcache_present) && core_config_dcache_present == 1
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#define ARC_FEATURE_DCACHE_PRESENT 1
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#define ARC_FEATURE_DCACHE_BUILD core_config_bcr_d_cache_build
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#define ARC_FEATURE_DCACHE_BUILD_VERSION core_config_bcr_d_cache_build_version
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#define ARC_FEATURE_DCACHE_BUILD_ASSOC core_config_bcr_d_cache_build_assoc
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#define ARC_FEATURE_DCACHE_BUILD_CAPACITY core_config_bcr_d_cache_build_capacity
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#define ARC_FEATURE_DCACHE_BUILD_BSIZE core_config_bcr_d_cache_build_bsize
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#define ARC_FEATURE_DCACHE_BUILD_FL core_config_bcr_d_cache_build_fl
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#define ARC_FEATURE_DCACHE_BUILD_U core_config_bcr_d_cache_build_u
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#define ARC_FEATURE_DCACHE_SIZE core_config_dcache_size
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#define ARC_FEATURE_DCACHE_LINE_SIZE core_config_dcache_line_size
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#define ARC_FEATURE_DCACHE_WAYS core_config_dcache_ways
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#define ARC_FEATURE_DCACHE_FEATURE core_config_dcache_feature
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/** Instruction Cache options */
|
||
|
|
#if !defined(ARC_FEATURE_ICACHE_PRESENT)
|
||
|
|
#if defined(core_config_icache_present) && core_config_icache_present == 1
|
||
|
|
#define ARC_FEATURE_ICACHE_PRESENT 1
|
||
|
|
#define ARC_FEATURE_ICACHE_BUILD core_config_bcr_i_cache_build
|
||
|
|
#define ARC_FEATURE_ICACHE_BUILD_VERSION core_config_bcr_i_cache_build_version
|
||
|
|
#define ARC_FEATURE_ICACHE_BUILD_ASSOC core_config_bcr_i_cache_build_assoc
|
||
|
|
#define ARC_FEATURE_ICACHE_BUILD_CAPACITY core_config_bcr_i_cache_build_capacity
|
||
|
|
#define ARC_FEATURE_ICACHE_BUILD_BSIZE core_config_bcr_i_cache_build_bsize
|
||
|
|
#define ARC_FEATURE_ICACHE_BUILD_FL core_config_bcr_i_cache_build_fl
|
||
|
|
#define ARC_FEATURE_ICACHE_BUILD_D core_config_bcr_i_cache_build_d
|
||
|
|
#define ARC_FEATURE_ICACHE_SIZE core_config_icache_size
|
||
|
|
#define ARC_FEATURE_ICACHE_LINE_SIZE core_config_icache_line_size
|
||
|
|
#define ARC_FEATURE_ICACHE_WAYS core_config_icache_ways
|
||
|
|
#define ARC_FEATURE_ICACHE_FEATURE core_config_icache_feature
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/** ARC uDMA options */
|
||
|
|
#if !defined(ARC_FEATURE_DMAC)
|
||
|
|
#if defined(core_config_dmac)
|
||
|
|
#define ARC_FEATURE_DMAC core_config_dmac
|
||
|
|
#define CORE_DMAC_CHANNELS core_config_dmac_channels
|
||
|
|
#define CORE_DMAC_REGISTERS core_config_dmac_registers
|
||
|
|
#if core_config_bcr_dmac_build_int_cfg == 2 && core_config_bcr_dmac_build_int_cfg == 4
|
||
|
|
#define DMA_MULTI_IRQ 1
|
||
|
|
#else
|
||
|
|
#define DMA_MULTI_IRQ 0
|
||
|
|
#endif
|
||
|
|
#define ARC_FEATURE_DMAC_PRESENT core_config_dmac
|
||
|
|
#define ARC_FEATURE_DMAC_VERSION core_config_bcr_dmac_build_version
|
||
|
|
#define ARC_FEATURE_DMAC_CHANNELS core_config_dmac_channels
|
||
|
|
#define ARC_FEATURE_DMAC_REGISTERS core_config_dmac_registers
|
||
|
|
#define ARC_FEATURE_DMAC_INT_CFG core_config_bcr_dmac_build_int_cfg
|
||
|
|
#define ARC_FEATURE_DMAC_FIFO_DEPTH core_config_dmac_fifo_depth
|
||
|
|
|
||
|
|
#ifdef ARC_FEATURE_SEC_TIMER0_PRESENT
|
||
|
|
#define DMA_IRQ_NUM_START 22
|
||
|
|
#define ARC_FEATURE_DMAC_VECTOR_START 22
|
||
|
|
#else
|
||
|
|
#define DMA_IRQ_NUM_START 20
|
||
|
|
#define ARC_FEATURE_DMAC_VECTOR_START 20
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
extern "C" {
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef ARC_FEATURE_UNALIGNED
|
||
|
|
#define STATUS32_RESET_VALUE (1<<19)
|
||
|
|
#else
|
||
|
|
#define STATUS32_RESET_VALUE (0)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _ARC_FEATURE_CONFIG_H_ */
|
||
|
|
|
||
|
|
/** @} */
|