2021-08-21 14:10:33 +08:00
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/*
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2021-09-07 12:42:29 +08:00
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* Copyright (C) 2021, Huada Semiconductor Co., Ltd.
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2021-08-21 14:10:33 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2021-09-07 12:42:29 +08:00
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* 2021-08-19 pjq first version
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2021-08-21 14:10:33 +08:00
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*/
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#include <rtthread.h>
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#include "rthw.h"
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#ifdef RT_USING_PIN
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#include "gpio.h"
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#include "drv_gpio.h"
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#include "interrupts_hc32l136.h"
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#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F))
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#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) * 0x40u))
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#define GPIO_PIN(pin) ((uint16_t)(GPIO_PIN_INDEX(pin)))
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#define PIN_NUM(port, pin) (((((port) / 0x40u) << 4) | ((pin) & 0x0F)))
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#define PIN_MAX_NUM ((GpioPortD / 0x40u * 16) + (GpioPin15 + 1))
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static void pin_irq_handler(en_gpio_port_t port, en_gpio_pin_t pin)
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{
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rt_int32_t irqindex = -1;
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irqindex = PIN_NUM(port, pin);
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if (pin_irq_hdr_tab[irqindex].hdr)
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{
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pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
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}
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}
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void Gpio_IRQHandler(uint8_t u8Param)
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{
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en_gpio_pin_t i;
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en_gpio_port_t enPort;
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enPort = (en_gpio_port_t)(GpioPortA + (GpioPortB - GpioPortA) * u8Param);
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rt_interrupt_enter();
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for (i=GpioPin0; i<=GpioPin15; i++)
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{
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if(TRUE == Gpio_GetIrqStatus(enPort, i))
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{
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Gpio_ClearIrq(enPort, i);
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pin_irq_handler(enPort, i);
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}
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}
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rt_interrupt_leave();
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}
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2021-09-07 12:42:29 +08:00
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static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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2021-08-21 14:10:33 +08:00
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{
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uint8_t gpio_port;
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uint16_t gpio_pin;
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if (pin < PIN_MAX_NUM)
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{
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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if (PIN_LOW == value)
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{
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Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, FALSE);
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}
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else
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{
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Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, TRUE);
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}
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}
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}
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2021-09-07 12:42:29 +08:00
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static int _pin_read(rt_device_t dev, rt_base_t pin)
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2021-08-21 14:10:33 +08:00
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{
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uint8_t gpio_port;
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uint16_t gpio_pin;
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int value = PIN_LOW;
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if (pin < PIN_MAX_NUM)
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{
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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if (FALSE == Gpio_GetInputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin))
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{
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value = PIN_LOW;
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}
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else
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{
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value = PIN_HIGH;
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}
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}
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return value;
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}
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2021-09-07 12:42:29 +08:00
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static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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2021-08-21 14:10:33 +08:00
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{
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uint8_t gpio_port;
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uint16_t gpio_pin;
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stc_gpio_config_t pstcGpioCfg;
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memset(&pstcGpioCfg, 0, sizeof(pstcGpioCfg));
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if (pin >= PIN_MAX_NUM)
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{
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return;
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}
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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pstcGpioCfg.enDir = GpioDirOut;
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pstcGpioCfg.enDrv = GpioDrvL;
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pstcGpioCfg.enCtrlMode = GpioAHB;
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break;
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case PIN_MODE_INPUT:
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pstcGpioCfg.enDir = GpioDirIn;
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pstcGpioCfg.enDrv = GpioDrvL;
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pstcGpioCfg.enPuPd = GpioPu;
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pstcGpioCfg.enOD = GpioOdDisable;
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pstcGpioCfg.enCtrlMode = GpioAHB;
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break;
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case PIN_MODE_INPUT_PULLUP:
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pstcGpioCfg.enDir = GpioDirIn;
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pstcGpioCfg.enDrv = GpioDrvL;
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pstcGpioCfg.enPuPd = GpioPu;
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pstcGpioCfg.enOD = GpioOdDisable;
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pstcGpioCfg.enCtrlMode = GpioAHB;
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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pstcGpioCfg.enDir = GpioDirIn;
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pstcGpioCfg.enDrv = GpioDrvL;
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pstcGpioCfg.enPuPd = GpioPd;
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pstcGpioCfg.enOD = GpioOdDisable;
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pstcGpioCfg.enCtrlMode = GpioAHB;
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break;
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case PIN_MODE_OUTPUT_OD:
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pstcGpioCfg.enDir = GpioDirOut;
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pstcGpioCfg.enDrv = GpioDrvL;
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pstcGpioCfg.enOD = GpioOdEnable;
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pstcGpioCfg.enCtrlMode = GpioAHB;
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break;
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default:
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break;
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}
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg);
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}
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2021-09-07 12:42:29 +08:00
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static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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2021-08-21 14:10:33 +08:00
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (pin >= PIN_MAX_NUM)
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{
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return -RT_ENOSYS;
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}
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irqindex = pin;
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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2021-09-07 12:42:29 +08:00
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static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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2021-08-21 14:10:33 +08:00
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (pin >= PIN_MAX_NUM)
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{
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return -RT_ENOSYS;
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}
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irqindex = pin;
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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2021-09-07 12:42:29 +08:00
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static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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2021-08-21 14:10:33 +08:00
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{
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rt_base_t level;
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en_gpio_port_t gpio_port;
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en_gpio_pin_t gpio_pin;
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rt_int32_t irqindex;
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stc_gpio_config_t pstcGpioCfg;
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if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled)))
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{
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return -RT_ENOSYS;
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}
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irqindex = pin;
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gpio_port = (en_gpio_port_t)GPIO_PORT(pin);
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gpio_pin = (en_gpio_pin_t)GPIO_PIN(pin);
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if (enabled == PIN_IRQ_ENABLE)
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{
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
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}
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/* Exint config */
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pstcGpioCfg.enDir = GpioDirIn;
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pstcGpioCfg.enDrv = GpioDrvL;
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pstcGpioCfg.enPuPd = GpioPu;
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pstcGpioCfg.enOD = GpioOdDisable;
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pstcGpioCfg.enCtrlMode = GpioAHB;
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Gpio_Init(gpio_port, gpio_pin, &pstcGpioCfg);
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Gpio_ClearIrq(gpio_port, gpio_pin);
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqRising);
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break;
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case PIN_IRQ_MODE_FALLING:
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Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqFalling);
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqHigh);
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqLow);
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break;
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}
|
|
|
|
EnableNvic((IRQn_Type)(pin / 16), IrqLevel3, TRUE);
|
|
|
|
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
level = rt_hw_interrupt_disable();
|
|
|
|
switch (pin_irq_hdr_tab[irqindex].mode)
|
|
|
|
{
|
|
|
|
case PIN_IRQ_MODE_RISING:
|
|
|
|
Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqRising);
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_FALLING:
|
|
|
|
Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling);
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
|
|
|
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_LOW_LEVEL:
|
|
|
|
Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqLow);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
}
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
2021-09-07 12:42:29 +08:00
|
|
|
static const struct rt_pin_ops _pin_ops =
|
2021-08-21 14:10:33 +08:00
|
|
|
{
|
2021-09-07 12:42:29 +08:00
|
|
|
_pin_mode,
|
|
|
|
_pin_write,
|
|
|
|
_pin_read,
|
|
|
|
_pin_attach_irq,
|
|
|
|
_pin_detach_irq,
|
|
|
|
_pin_irq_enable,
|
2021-08-21 14:10:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
int rt_hw_pin_init(void)
|
|
|
|
{
|
|
|
|
Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE);
|
|
|
|
|
2021-09-07 12:42:29 +08:00
|
|
|
return rt_device_pin_register("pin", &_pin_ops, RT_NULL);
|
2021-08-21 14:10:33 +08:00
|
|
|
}
|
|
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
|
|
|
|
|
|
|
#endif /* RT_USING_PIN */
|