462 lines
13 KiB
C
462 lines
13 KiB
C
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/**************************************************************************//**
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* @file i2s.c
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* @brief N9H30 I2S driver source file
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*
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* @note
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "N9H30.h"
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#include "nu_sys.h"
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#include "nu_i2s.h"
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/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
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@{
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*/
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/** @addtogroup N9H30_I2S_Driver I2S Driver
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@{
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*/
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/** @addtogroup N9H30_I2S_EXPORTED_CONSTANTS I2S Exported Constants
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@{
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*/
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/// @cond HIDDEN_SYMBOLS
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typedef uint32_t (AU_CB_FUNC_T)(uint32_t);
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static AU_CB_FUNC_T *g_fnPlayCallBack;
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static AU_CB_FUNC_T *g_fnRecCallBack;
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static uint8_t i2sOpened = 0;
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/// @endcond /* HIDDEN_SYMBOLS */
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/*@}*/ /* end of group N9H30_I2S_EXPORTED_CONSTANTS */
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/** @addtogroup N9H30_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
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@{
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*/
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/// @cond HIDDEN_SYMBOLS
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/**
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* @brief Start to play
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* @param None
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* @return None
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*/
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static void i2sStartPlay(void)
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{
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/* start playing */
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//sysprintf("IIS start playing...\n");
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outpw(REG_ACTL_PSR, 0x1);
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (1 << 5));
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}
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/**
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* @brief Stop to play
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* @param None
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* @return None
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*/
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static void i2sStopPlay(void)
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{
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//sysprintf("IIS stop playing\n");
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/* stop playing */
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(1 << 5));
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}
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/**
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* @brief Start to record
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* @param None
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* @return None
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*/
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static void i2sStartRecord(void)
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{
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/* start recording */
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//sysprintf("IIS start recording...\n");
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outpw(REG_ACTL_RSR, 0x1);
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (1 << 6));
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}
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/**
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* @brief Stop to record
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* @param None
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* @return None
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*/
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static void i2sStopRecord(void)
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{
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//sysprintf("I2S stop recording\n");
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/* stop recording */
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(1 << 6));
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}
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/**
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* @brief Delay function
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* @param None
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* @return None
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*/
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static void Delay(int nCnt)
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{
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int volatile loop;
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for (loop = 0; loop < nCnt * 10; loop++);
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}
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/**
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* @brief Interrupt service routine for i2s
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* @param None
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* @return None
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*/
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static void i2sISR(void)
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{
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uint8_t u8SN;
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if (inpw(REG_ACTL_CON) & (1 << 10))
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{
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outpw(REG_ACTL_CON, inpw(REG_ACTL_CON) | (1 << 10)); //Clear TX INT
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if (inpw(REG_ACTL_PSR) & (1 << 4))
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{
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outpw(REG_ACTL_PSR, (1 << 4));
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//sysprintf("\ndebug:DMA_COUNTER_IRQ occur");
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}
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if (inpw(REG_ACTL_PSR) & (1 << 3))
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{
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outpw(REG_ACTL_PSR, (1 << 3));
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//sysprintf("\ndebug:DMA_DATA_ZERO_IRQ occur");
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}
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if (inpw(REG_ACTL_PSR) & 0x1)
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{
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outpw(REG_ACTL_PSR, 0x1);
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u8SN = (inpw(REG_ACTL_PSR) >> 5) & 0x7;
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g_fnPlayCallBack(u8SN);
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}
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}
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if (inpw(REG_ACTL_CON) & (1 << 11))
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{
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outpw(REG_ACTL_CON, inpw(REG_ACTL_CON) | (1 << 11)); //Clear RX INT
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if (inpw(REG_ACTL_RSR) & 0x1)
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{
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outpw(REG_ACTL_RSR, 0x1);
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u8SN = (inpw(REG_ACTL_RSR) >> 5) & 0x7;
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g_fnRecCallBack(u8SN);
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}
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}
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}
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/// @endcond /* HIDDEN_SYMBOLS */
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/**
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* @brief Open i2s interface
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* @return open status
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* @retval I2S_ERR_BUSY error.
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* @retval 0 success.
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*/
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int32_t i2sOpen(void)
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{
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if (i2sOpened)
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return I2S_ERR_BUSY;
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/* reset audio interface */
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (1 << 16));
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Delay(100);
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(1 << 16));
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Delay(100);
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/* reset IIS interface */
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | 0x1);
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Delay(100);
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~0x1);
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Delay(100);
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outpw(REG_ACTL_CON, inpw(REG_ACTL_CON) | (1 << 21) | (1 << 20));
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i2sOpened = 1;
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return 0;
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}
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/**
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* @brief Close i2s interface
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* @return None
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*/
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void i2sClose(void)
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{
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// reset some variables
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i2sOpened = 0;
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g_fnPlayCallBack = NULL;
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g_fnRecCallBack = NULL;
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// reset i2s interface
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outpw(REG_SYS_AHBIPRST, inpw(REG_SYS_AHBIPRST) | (1 << 8));
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outpw(REG_SYS_AHBIPRST, inpw(REG_SYS_AHBIPRST) & ~(1 << 8));
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}
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/**
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* @brief Initialize i2s interface and setup interrupt
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* @return None
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*/
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void i2sInit(void)
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{
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// enable i2s engine clock
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outpw(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) | (1 << 24));
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// enable interrupt and set ISR
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sysSetInterruptType(ACTL_IRQn, HIGH_LEVEL_SENSITIVE);
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sysInstallISR(IRQ_LEVEL_1, ACTL_IRQn, (PVOID)i2sISR);
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sysEnableInterrupt(ACTL_IRQn);
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sysSetLocalInterrupt(ENABLE_IRQ);
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}
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/**
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* @brief IO control for i2s interface
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* @param[in] cmd Command for io control, value could be
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* - \ref I2S_SET_PLAY
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* - \ref I2S_SET_RECORD
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* - \ref I2S_SELECT_BLOCK
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* - \ref I2S_SELECT_BIT
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* - \ref I2S_SET_PLAY_DMA_INT_SEL
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* - \ref I2S_SET_REC_DMA_INT_SEL
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* - \ref I2S_SET_ZEROCROSS
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* - \ref I2S_SET_DMACOUNTER
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* - \ref I2S_SET_CHANNEL
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* - \ref I2S_SET_MODE
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* - \ref I2S_SET_SPLITDATA
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* - \ref I2S_SET_DMA_ADDRESS
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* - \ref I2S_SET_DMA_LENGTH
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* - \ref I2S_GET_DMA_CUR_ADDRESS
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* - \ref I2S_SET_I2S_FORMAT
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* - \ref I2S_SET_I2S_CALLBACKFUN
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* - \ref I2S_SET_PCMSLOT
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* @param[in] arg0 argument 0 for io control
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* @param[in] arg1 argument 1 for io control
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* @retval I2S_ERR_IO Command error.
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* @retval 0 success.
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*/
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int32_t i2sIoctl(uint32_t cmd, uint32_t arg0, uint32_t arg1)
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{
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uint32_t *buf;
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AU_CB_FUNC_T *ptr;
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switch (cmd)
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{
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// #define I2S_START_PLAY 0
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// #define I2S_STOP_PLAY 1
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case I2S_SET_PLAY:
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if (arg0 == I2S_START_PLAY)
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i2sStartPlay();
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else
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i2sStopPlay();
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break;
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// #define I2S_START_REC 0
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// #define I2S_STOP_REC 1
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case I2S_SET_RECORD:
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if (arg0 == I2S_START_REC)
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i2sStartRecord();
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else
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i2sStopRecord();
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break;
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// #define I2S_BLOCK_I2S 0
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// #define I2S_BLOCK_PCM 1
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case I2S_SELECT_BLOCK:
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if (arg0 == I2S_BLOCK_I2S)
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outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x3) | 0x1);
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else
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outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x3) | 0x2);
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break;
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// #define I2S_BIT_WIDTH_8 0
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// #define I2S_BIT_WIDTH_16 1
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// #define I2S_BIT_WIDTH_24 2
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case I2S_SELECT_BIT:
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outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x300) | (arg0 << 8));
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break;
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// #define I2S_DMA_INT_END 0
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// #define I2S_DMA_INT_HALF 1
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// #define I2S_DMA_INT_QUARTER 2
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// #define I2S_DMA_INT_EIGTH 3
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case I2S_SET_PLAY_DMA_INT_SEL:
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outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0x3000) | (arg0 << 12));
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break;
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case I2S_SET_REC_DMA_INT_SEL:
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outpw(REG_ACTL_CON, (inpw(REG_ACTL_CON) & ~0xc000) | (arg0 << 14));
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break;
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case I2S_SET_ZEROCROSS:
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if (arg0 == I2S_ENABLE)
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | 0x8);
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else
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~0x8);
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break;
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case I2S_SET_DMACOUNTER:
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if (arg0 == I2S_ENABLE)
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | 0x10);
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else
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~0x10);
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break;
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// #define I2S_CHANNEL_I2S_ONE 2
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// #define I2S_CHANNEL_I2S_TWO 3
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// #define I2S_CHANNEL_PCM_TWO 3
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// #define I2S_CHANNEL_PCM_TWO_SLOT1 0
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// #define I2S_CHANNEL_PCM_TWO_SLOT0 1
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// #define I2S_CHANNEL_PCM_ONE_SLOT0 2
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case I2S_SET_CHANNEL:
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if (arg0 == I2S_PLAY)
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(0x3 << 12) | (arg1 << 12));
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else
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(0x3 << 14) | (arg1 << 14));
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break;
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// #define I2S_MODE_MASTER 0
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// #define I2S_MODE_SLAVE 1
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case I2S_SET_MODE:
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if (arg0 == I2S_MODE_MASTER)
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outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) & ~(0x1 << 20));
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else
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outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) | (0x1 << 20));
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break;
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case I2S_SET_SPLITDATA:
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if (arg0 == I2S_ENABLE)
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) | (0x1 << 20));
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else
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outpw(REG_ACTL_RESET, inpw(REG_ACTL_RESET) & ~(0x1 << 20));
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break;
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case I2S_SET_DMA_ADDRESS:
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if (arg0 == I2S_PLAY)
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outpw(REG_ACTL_PDESB, arg1 | 0x80000000);
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else if (arg0 == I2S_REC)
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outpw(REG_ACTL_RDESB, arg1 | 0x80000000);
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else if (arg0 == PCM_PLAY)
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outpw(REG_ACTL_PDESB2, arg1 | 0x80000000);
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else
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outpw(REG_ACTL_RDESB2, arg1 | 0x80000000);
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break;
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case I2S_SET_DMA_LENGTH:
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if (arg0 == I2S_PLAY)
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outpw(REG_ACTL_PDES_LENGTH, arg1);
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else
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outpw(REG_ACTL_RDES_LENGTH, arg1);
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break;
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case I2S_GET_DMA_CUR_ADDRESS:
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buf = (uint32_t *)arg0;
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if (arg0 == I2S_PLAY)
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*buf = inpw(REG_ACTL_PDESC);
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else
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*buf = inpw(REG_ACTL_RDESC);
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break;
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|
|
||
|
|
// #define I2S_FORMAT_I2S 0
|
||
|
|
// #define I2S_FORMAT_MSB 1
|
||
|
|
case I2S_SET_I2S_FORMAT:
|
||
|
|
if (arg0 == I2S_FORMAT_I2S)
|
||
|
|
outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) & ~ 0x8);
|
||
|
|
else
|
||
|
|
outpw(REG_ACTL_I2SCON, inpw(REG_ACTL_I2SCON) | 0x8);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case I2S_SET_I2S_CALLBACKFUN:
|
||
|
|
ptr = (AU_CB_FUNC_T *)arg1;
|
||
|
|
if (arg0 == I2S_PLAY)
|
||
|
|
g_fnPlayCallBack = ptr;
|
||
|
|
else
|
||
|
|
g_fnRecCallBack = ptr;
|
||
|
|
break;
|
||
|
|
// #define PCM_SLOT1_IN 0
|
||
|
|
// #define PCM_SLOT1_OUT 1
|
||
|
|
// #define PCM_SLOT2_IN 2
|
||
|
|
// #define PCM_SLOT2_OUT 3
|
||
|
|
case I2S_SET_PCMSLOT:
|
||
|
|
if (arg0 == PCM_SLOT1_IN)
|
||
|
|
outpw(REG_ACTL_PCMS1ST, (inpw(REG_ACTL_PCMS1ST) & ~0x3ff) | (arg1 & 0x3ff));
|
||
|
|
else if (arg0 == PCM_SLOT1_OUT)
|
||
|
|
outpw(REG_ACTL_PCMS1ST, (inpw(REG_ACTL_PCMS1ST) & ~0x3ff0000) | ((arg1 & 0x3ff) << 16));
|
||
|
|
else if (arg0 == PCM_SLOT2_IN)
|
||
|
|
outpw(REG_ACTL_PCMS2ST, (inpw(REG_ACTL_PCMS2ST) & ~0x3ff) | (arg1 & 0x3ff));
|
||
|
|
else
|
||
|
|
outpw(REG_ACTL_PCMS2ST, (inpw(REG_ACTL_PCMS2ST) & ~0x3ff0000) | ((arg1 & 0x3ff) << 16));
|
||
|
|
break;
|
||
|
|
|
||
|
|
case I2S_SET_PCM_FS_PERIOD:
|
||
|
|
outpw(REG_ACTL_PCMCON, (inpw(REG_ACTL_PCMCON) & ~0x03FF0000 | (((arg0 - 1) & 0x3ff) << 16)));
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return I2S_ERR_IO;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configure sampling rate for audio
|
||
|
|
* @param[in] u32SourceClockRate source speed to i2s interface
|
||
|
|
* @param[in] u32SampleRate sampling rate
|
||
|
|
* @param[in] u32DataBit data width
|
||
|
|
* @param[in] u32Channel channel number
|
||
|
|
* @return None
|
||
|
|
*/
|
||
|
|
void i2sSetSampleRate(uint32_t u32SourceClockRate, uint32_t u32SampleRate, uint32_t u32DataBit, uint32_t u32Channel)
|
||
|
|
{
|
||
|
|
uint32_t u32BCLKDiv;
|
||
|
|
uint32_t u32MCLK, u32MCLKDiv;
|
||
|
|
|
||
|
|
u32MCLK = (u32SampleRate * 256);
|
||
|
|
u32MCLKDiv = u32SourceClockRate / u32MCLK;
|
||
|
|
outpw(REG_ACTL_I2SCON, (inpw(REG_ACTL_I2SCON) & ~0x000F0000) | (u32MCLKDiv - 1) << 16);
|
||
|
|
|
||
|
|
u32BCLKDiv = u32MCLK / (u32SampleRate * u32DataBit * u32Channel);
|
||
|
|
u32BCLKDiv = u32BCLKDiv / 2 - 1;
|
||
|
|
outpw(REG_ACTL_I2SCON, (inpw(REG_ACTL_I2SCON) & ~0xF0) | u32BCLKDiv << 5);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configure MCLK frequency (master mode)
|
||
|
|
* @param[in] u32SourceClockRate source clock rate
|
||
|
|
* @param[in] u32SampleRate sampling rate
|
||
|
|
* @return None
|
||
|
|
*/
|
||
|
|
void i2sSetMCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32SampleRate)
|
||
|
|
{
|
||
|
|
uint32_t u32MCLK, u32MCLKDiv;
|
||
|
|
|
||
|
|
u32MCLK = (u32SampleRate * 256);
|
||
|
|
u32MCLKDiv = u32SourceClockRate / u32MCLK;
|
||
|
|
outpw(REG_ACTL_I2SCON, (inpw(REG_ACTL_I2SCON) & ~0x000F0000) | (u32MCLKDiv - 1) << 16);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configure PCM BCLK frequency (master mode)
|
||
|
|
* @param[in] u32SourceClockRate source clock rate
|
||
|
|
* @param[in] u32Rate target rate
|
||
|
|
* @return None
|
||
|
|
*/
|
||
|
|
void i2sSetPCMBCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32Rate)
|
||
|
|
{
|
||
|
|
uint32_t u32BCLKDiv;
|
||
|
|
|
||
|
|
u32BCLKDiv = (u32SourceClockRate / (2 * u32Rate)) - 1;
|
||
|
|
outpw(REG_ACTL_PCMCON, (inpw(REG_ACTL_PCMCON) & ~0x0000FF00) | (u32BCLKDiv << 8));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*@}*/ /* end of group N9H30_I2S_EXPORTED_FUNCTIONS */
|
||
|
|
|
||
|
|
/*@}*/ /* end of group N9H30_I2S_Driver */
|
||
|
|
|
||
|
|
/*@}*/ /* end of group N9H30_Device_Driver */
|
||
|
|
|
||
|
|
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||
|
|
|