382 lines
29 KiB
C
382 lines
29 KiB
C
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/*!
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\file gd32f10x.h
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\brief general definitions for GD32F10x
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_H
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#define GD32F10X_H
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#ifdef cplusplus
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extern "C" {
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#endif
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/* define GD32F10x */
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#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL)
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/* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */
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/* #define GD32F10X_HD */ /*!< GD32F10X_HD: GD32 High density Value Line devices */
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/* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */
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/* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */
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#endif /* define GD32F10x */
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#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL)
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#error "Please select the target GD32F10x device in gd32f10x.h file"
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#endif /* undefine GD32F10x tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined HXTAL_VALUE
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#ifdef GD32F10X_CL
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#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
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#else
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#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
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#endif /* HXTAL_VALUE */
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
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#if !defined (IRC8M_VALUE)
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#define IRC8M_VALUE ((uint32_t)8000000)
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#endif /* internal 8MHz RC oscillator value */
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/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
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#if !defined (IRC8M_STARTUP_TIMEOUT)
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#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 8MHz RC oscillator startup timeout */
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/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
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#if !defined (IRC40K_VALUE)
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#define IRC40K_VALUE ((uint32_t)40000)
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#endif /* internal 40KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* GD32F10x firmware library version number V2.0 */
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#define __GD32F10x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __GD32F10x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __GD32F10x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __GD32F10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32F10x_STDPERIPH_VERSION ((__GD32F10x_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32F10x_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32F10x_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32F10x_STDPERIPH_VERSION_RC))
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/* configuration of the Cortex-M3 processor and core peripherals */
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#define __MPU_PRESENT 0 /*!< GD32F10x do not provide MPU */
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#define __NVIC_PRIO_BITS 4 /*!< GD32F10x uses 4 bits for the priority levels */
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#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
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/* define interrupt number */
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typedef enum IRQn
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{
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/* Cortex-M3 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 memory management interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 bus fault interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 usage fault interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV call interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 debug monitor interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 pend SV interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
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LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
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TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
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RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
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FMC_IRQn = 4, /*!< FMC interrupt */
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RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
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EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
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EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
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EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
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EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
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EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
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DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
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DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
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DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
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DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
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DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
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DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
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DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
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ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
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#ifdef GD32F10X_MD
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USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
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USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
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CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
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CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
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EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
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TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
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TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 interrupt */
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USART1_IRQn = 38, /*!< USART1 interrupt */
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USART2_IRQn = 39, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
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USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
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EXMC_IRQn = 48, /*!< EXMC global interrupt */
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#endif /* GD32F10X_MD */
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#ifdef GD32F10X_HD
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USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
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USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
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CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
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CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
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EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
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TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
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TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 interrupt */
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USART1_IRQn = 38, /*!< USART1 interrupt */
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USART2_IRQn = 39, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
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USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
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TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */
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TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */
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TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */
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TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */
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ADC2_IRQn = 47, /*!< ADC2 global interrupt */
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EXMC_IRQn = 48, /*!< EXMC global interrupt */
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SDIO_IRQn = 49, /*!< SDIO global interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
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SPI2_IRQn = 51, /*!< SPI2 global interrupt */
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UART3_IRQn = 52, /*!< UART3 global interrupt */
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UART4_IRQn = 53, /*!< UART4 global interrupt */
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TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
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TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
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DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
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#endif /* GD32F10X_HD */
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#ifdef GD32F10X_XD
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USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
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USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
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CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
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CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
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EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
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TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
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TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
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TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 interrupt */
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USART1_IRQn = 38, /*!< USART1 interrupt */
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USART2_IRQn = 39, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
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USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
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TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
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TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
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TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
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TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */
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ADC2_IRQn = 47, /*!< ADC2 global interrupt */
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EXMC_IRQn = 48, /*!< EXMC global interrupt */
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SDIO_IRQn = 49, /*!< SDIO global interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
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SPI2_IRQn = 51, /*!< SPI2 global interrupt */
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UART3_IRQn = 52, /*!< UART3 global interrupt */
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UART4_IRQn = 53, /*!< UART4 global interrupt */
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TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
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TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
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DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
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#endif /* GD32F10X_XD */
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#ifdef GD32F10X_CL
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CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
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CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
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CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
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CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
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EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
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TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
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TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 interrupt */
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USART1_IRQn = 38, /*!< USART1 interrupt */
|
||
|
|
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||
|
|
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||
|
|
RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */
|
||
|
|
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
||
|
|
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */
|
||
|
|
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */
|
||
|
|
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */
|
||
|
|
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */
|
||
|
|
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||
|
|
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||
|
|
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||
|
|
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||
|
|
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||
|
|
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||
|
|
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||
|
|
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||
|
|
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||
|
|
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||
|
|
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
|
||
|
|
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
|
||
|
|
ENET_IRQn = 61, /*!< ENET global interrupt */
|
||
|
|
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
||
|
|
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||
|
|
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||
|
|
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||
|
|
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||
|
|
USBFS_IRQn = 67, /*!< USBFS global interrupt */
|
||
|
|
#endif /* GD32F10X_CL */
|
||
|
|
|
||
|
|
} IRQn_Type;
|
||
|
|
|
||
|
|
/* includes */
|
||
|
|
#include "core_cm3.h"
|
||
|
|
#include "system_gd32f10x.h"
|
||
|
|
#include <stdint.h>
|
||
|
|
|
||
|
|
/* enum definitions */
|
||
|
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||
|
|
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
|
||
|
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||
|
|
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||
|
|
|
||
|
|
/* bit operations */
|
||
|
|
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||
|
|
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||
|
|
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||
|
|
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||
|
|
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||
|
|
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||
|
|
|
||
|
|
/* main flash and SRAM memory map */
|
||
|
|
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||
|
|
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||
|
|
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||
|
|
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||
|
|
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||
|
|
|
||
|
|
/* peripheral memory map */
|
||
|
|
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||
|
|
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||
|
|
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
|
||
|
|
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
|
||
|
|
|
||
|
|
/* advanced peripheral bus 1 memory map */
|
||
|
|
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||
|
|
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||
|
|
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||
|
|
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||
|
|
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||
|
|
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||
|
|
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||
|
|
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
|
||
|
|
#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */
|
||
|
|
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||
|
|
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
|
||
|
|
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||
|
|
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||
|
|
|
||
|
|
/* advanced peripheral bus 2 memory map */
|
||
|
|
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
|
||
|
|
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||
|
|
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
|
||
|
|
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||
|
|
|
||
|
|
/* advanced high performance bus 1 memory map */
|
||
|
|
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
|
||
|
|
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
|
||
|
|
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
|
||
|
|
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
|
||
|
|
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
|
||
|
|
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
|
||
|
|
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
|
||
|
|
|
||
|
|
/* define marco USE_STDPERIPH_DRIVER */
|
||
|
|
#if !defined USE_STDPERIPH_DRIVER
|
||
|
|
#define USE_STDPERIPH_DRIVER
|
||
|
|
#endif
|
||
|
|
#ifdef USE_STDPERIPH_DRIVER
|
||
|
|
#include "gd32f10x_libopt.h"
|
||
|
|
#endif /* USE_STDPERIPH_DRIVER */
|
||
|
|
|
||
|
|
#ifdef cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#endif
|